The POWER6 will be using approximately 790 million transistors and 341 mm² large fabricated on an 65 nm process. It will be released 8th June 2007, at speeds of 3.5 Ghz, 4.2 Ghz and 4.7 Ghz, but the company has noted prototypes have reached 6 GHz. POWER6 reached first silicon in the middle of 2005. The processor is a dual core design and will have 128 KiB of L1 cache (64 KiB data + 64 KiB instruction), an eight-way, set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle. Each core will have a 4 MiB "semi shared" L2 cache, where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB large L3 cache which is off die, using an 80 GB/s bus. Each core will have two integer units, two binary floating-point units, and a decimal floating-point unit, and is capable of two way SMT. The binary floating-point unit incorporates many microarchitectures, logic, circuit, latch and integration techniques to achieve a 6-cycle, 13-FO4 pipeline, according to a company paper. The POWER6 will have support for decimal arithmetic. 50 new floating point instructions handle the decimal math and conversions between binary and decimal. This is a feature currently present in the processors powering IBM's System z and is a necessity in POWER6 if the eClipz-mission is to succeed. There will be an AltiVec unit to POWER6, and the processor will be fully compliant with the new Power ISA v.2.03 specification. POWER6 will also take advantage of ViVA-2, Virtual Vector Architecture, that enables the combination of several POWER6 nodes so act as a single Vector processor.

64 bit 5x1.5Ghz Core Power5 Linux 2.6.5-7.267-pseries64