I work as a Research Scientist at Intel Labs.
Before that, I completed a Ph.D. on Side-Channel and Fault Analysis of Cryptographic Implementations at Graz University of Technology.
My research interests include practical and theoretical aspects of information security.
On the practical side, I work on designing and attacking implementations of (post-quantum)
cryptography in hardware/software that come with protection mechanisms against physical attacks such as
power/fault analysis.
On the more theoretical side, I work on designing and analyzing cryptographic modes that provide high
resistance against physical attacks or the formal verification of algorithmic countermeasures against
physical attacks.
I am a co-author of ISAP, a lightweight authenticated encryption
scheme that gives strong guarantees against various kinds of physical attacks.
ISAP reached the final round of the NIST standardization process for
lightweight cryptography.
Selected publications
Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs (pdf)
Power Contracts: Provably Complete Power Leakage Models for Processors (pdf)
Statistical Ineffective Fault Attacks on Masked AES with Fault Countermeasures (pdf)
Protecting against Statistical Ineffective Fault Attacks (pdf)
Chosen Ciphertext k-Trace Attacks on Masked CCA2 Secure Kyber (pdf)
Selected open-source contributions
Hardware reference implementations of Ascon (git) and ISAP (git)
Optimized (protected) software implementations of Ascon (git) and ISAP (git)
A Fast and Compact Accelerator for Ascon and Friends (git)
Hardware design of Ascon with protection against power analysis (git)