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lion: RISC-V Core
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lion: RISC-V Core
Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.
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Downloads
- lion-0.4.0.1.tar.gz [browse] (Cabal source package)
- Package description (as included in the package)
Maintainer's Corner
For package maintainers and hackage trustees
Candidates
- No Candidates
| Versions [RSS] | 0.1.0.0, 0.2.0.0, 0.3.0.0, 0.4.0.0, 0.4.0.1 |
|---|---|
| Change log | CHANGELOG.md |
| Dependencies | base (>=4.13 && <4.21), clash-prelude (>=1.2.5 && <1.9), generic-monoid (>=0.1 && <0.2), ghc-typelits-extra, ghc-typelits-knownnat, ghc-typelits-natnormalise, ice40-prim (>=0.3 && <0.3.1.5), lens (>=4.19 && <5.4), mtl (>=2.2 && <2.4) [details] |
| License | BSD-3-Clause |
| Copyright | (c) 2021-2024 David Cox |
| Author | dopamane <standard.semiconductor@gmail.com> |
| Maintainer | dopamane <standard.semiconductor@gmail.com> |
| Uploaded | by dopamane at 2024-08-03T07:54:16Z |
| Category | Hardware |
| Bug tracker | https://github.com/standardsemiconductor/lion/issues |
| Source repo | head: git clone https://github.com/standardsemiconductor/lion |
| Distributions | |
| Downloads | 673 total (17 in the last 30 days) |
| Rating | 2.0 (votes: 1) [estimated by Bayesian average] |
| Your Rating |
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| Status | Docs uploaded by user [build log] All reported builds failed as of 2024-08-03 [all 2 reports] |
Readme for lion-0.4.0.1
[back to package description]Where Lions Roam: RISC-V on the VELDT
Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.
This repository contains four parts:
- The Lion library: a pipelined RISC-V core.
- lion-formal: formally verify the core using riscv-formal.
- lion-soc: a System-on-Chip demonstrating usage of the Lion core on the VELDT.
- lion-metric: Observe Yosys synthesis metrics on the Lion Core.
Lion library
Usage:
- Add
lionto build depends section of Cabal file - import module in source files
import Lion.Core
When connecting the core to memory and peripherals, ensure single cycle latency.
Clone the repository
git clone https://github.com/standardsemiconductor/lion.gitcd liongit submodule update --init
Features
Current Support
- Architecture: RV32I (no FENCE, ECALL, EBREAK)
- Configurable ALU adder and subtractor: use a generic (+) and (-) or SB_MAC16 hard IP
Future Support
All features will be added in a configurable manner extending the base RV32I configuration noted above
- Zicsr, Control and Status Register (CSR) Instructions
- CSR registers
- RV32IM
Check out the Lion Development project to see which features are in progress.