Stopwatch

A Simple Stopwatch implemented on an FPGA board using Verilog HDL.

Time elapsed counter testbench simulation

rst= 1 bit binary signal to reset count

clk = 1-bit binary signal to toggle count

ss = 6 bit register(stores upto 59D secs) to store the seconds elapsed.

mm = 6 bit register(stores upto 59D mins) to store the minutes elapsed.

Uses 40 Buffers and LUTs in total

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
README.md		README.md
time_elapsed.v		time_elapsed.v
time_elapsed_counter_schematic.PNG		time_elapsed_counter_schematic.PNG
time_elapsed_tb.v		time_elapsed_tb.v
waveforms.PNG		waveforms.PNG