CV

See the pdf version here

Education

  • M.S. in Robotics, Carnegie Mellon University, 2025(expected)
  • B.S. in Computer Science, Tsinghua University, 2023

Work experience

  • Fall 2022 - Spring 2023
    • Research Assistant, Tsinghua University, IIIS
    • Supervisor: Huazhe Xu
    • Research Topic: Vision Language Models for Visual RL
      • Designed a learning pipeline that could leverage the knowledge from large-scale pre-trained text-to-image generation models for example-based visual reinforcement learning.
  • Summer 2022
    • On-Site Research Assistant, Stanford University, CogAI & SVL Lab
    • Supervisor: Ruohan Zhang, Jiajun Wu, Fei-fei Li
    • Research Topic: Preference Learning
      • Implemented a sample-efficient and user-friendly preference learning framework and performed real-robot experiments with human users.
  • Fall 2021 - Spring 2021
    • Remote Research Assistant, Stanford University, CogAI Lab
    • Supervisor: Ruohan Zhang, Huazhe Xu, Jiajun Wu
    • Research Topic: Multi-task Imitation Learning
      • Proposed a novel concurrent multi-task imitation learning setting, and a bootstrapping learning algorithm for the problem.
  • Summer 2021
    • Maching Learning Intern, Microsoft, China
    • Supervisor: Tianqi Zhao(mentor), Fantasy Zhang(manager)
    • Research Topic: Large Language Generation Models
      • Designed a network structure combining BART with CVAE to perform sequence-to-sequence Ad-Title generation from landing pages.
  • Spring 2020 - Fall 2020
    • Research Assistant, Tsinghua University, ECE Department
    • Supervisor: He Tian
    • Research Topic: Hardware for ML
      • Developed a CBRAM model that can be used as an artificial synapse for neural networks.

Skills

  • C/C++
    • Object Oriented Programming
    • Qt for desiging programs with GUI
    • Multiprocessing packages including OpenMP, MPI
  • Python
    • Data Processing packages including numpy, pandas
    • Proficient in PyTorch
  • Java
    • Android Development
  • R
  • LaTeX
  • CUDA
  • Verilog/VHDL
  • Rust