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Part 4 of the Smart FPGA Nic, dealing with the OrderBook has been published. Go here to see more: https://fpganow.com/index.php/part-4-order-book/ Related source code: https://github.com/fpganow/arty_bats/tree/main/labview/arty/orderbook As I make updates to the code, mainly to make it prettier and easier for others to follow, I will make new a post for each change detailing all changes.  

I just created a 'Page' as opposed to a WordPress 'Post' documenting how I was able to parse BATS Market Data messages. This new style or format will be much better than my writing multiples posts.  Easier for the reader to find, and easier for me to find and to update an article. Anyway, look above, under the "SMART 'FPGA-NIC'" menu above to find Part 2: Parse BATS …

Related Source Repository: https://github.com/fpganow/vivado_scm Xilinx Vivado does not come with built-in source control.  If you are a Visual Studio user, or a IntelliJ IDEA or eclipse user, you may be familiar with using some sort of IDE-related source code control. Vivado has a different paradigm for source control: Export commands to re-generate the project as a tcl script. Add tcl and all related files to source-control After I …

So my workflow is as follows: Create IP in NI LabVIEW FPGA Export via FPGA IP Export Tool Creates a VHDL wrapper (.vhd) Places IP in Design Checkpoint (.dcp) file Open my Vivado Block Design Use or update the VHDL wrapper that uses the Design Checkpoint Synthesis, Implementation, and Run The NI LabVIEW FPGA IP Export utility provides you with 2 files, a design checkpoint and a wrapper …

I got something working – with live hardware plugged in to my network. I used the larger version of the Arty Artix-7 board, which cost $250 USD, and made my own custom reader for the LabVIEW FPGA Network library.  I did not implement network writing features, nor do anything with the payload.  Nevertheless, this is a Proof-of-Concept and can be used to make a nice FPGA accelerated network …

So I am dealing with the following scenarios: Scenario 1 – Genesys Zynq with SYZYGY SFP I have the Genesys Zynq UltraScale+ MPSoC 3EG board that does not provide direct access to the PHY pins, but has a SYZYGY port that I have plugged in to the SZG-DUALSFP module with an SFP connector. Scenario 2 – Arty A7 Artix-7 with 10/100 Mbit PHY I have the Arty A7 …

Here is the new plan: Step 1 – Create a design using a MicroBlaze processing system, enable a UART connection and listen on an AXI FIFO and dump packets to the screen as they are received in chunks of X bytes. Step 2 – Insert some LabVIEW FPGA code to send one packet of data every second. Step 3 – Replace this LabVIEW FPGA code to listen to …

I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board to the Digilent Genesys Zynq UltraScale MPSoC+ board. Why? Because I have a really old board that cost only $99 dollars that gives me direct access to the pins of an old 10/100 MBit PHY! That's the Arty Artix-35T mini board! Anyway… I found a corresponding NI "no …

So I spent some time to rebuild the out-of-box demo for the Genesys Zynq UltraScale MPSoC+ board.  Not everything worked for me right away, so I made this post to include all the things I did to get it to work.: My system: Windows 10 Windows Subsystem for Linux 2 Ubuntu 18.04 (<= Ubuntu 20 does not work unless you make a lot of changes) References: Schematics https://reference.digilentinc.com/_media/reference/programmable-logic/genesys-zu/genesys_zu-3eg_sch_public.pdf …

I went to the Opal Kelly website again and noticed that there are a lot of menu options that I previously did not notice at the top menu. I found a sample board that uses their SZG-DUALSFP board: https://opalkelly.com/products/xem7320/ So now I can read the documentation for this board and be on my way! I also had some fun reading the specification documents for the SYZYGY specification, the …

So I have the Genesys Zynq UltraScale + MPSoC board, I bought the SZG-DUALSFP from Opel Kelly, and I want to figure out how to wire this thing up. What pin goes where? I dunno.  I spent some time reading the SFP+ specification.  Everything makes sense.  Then I read through the SYZYGY specification.  Again, things make sense. So what does the interface look like? Anybody know? One though …

After my previous post showing how to use the NI LabVIEW FPGA IP Export Utility to run LabVIEW FPGA code on a Zynqberry (https://fpganow.com/index.php/2020/09/28/zynqberry-with-breakout-board-and-labview/), I continued following the examples I could find on the internet and was able to connect to the board by using the PS (Processing System) built-int UART, and to communicate to the GPIO by using C code. Then I wanted to access the PHY …