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HTTP/2 200 server: GitHub.com content-type: text/html; charset=utf-8 last-modified: Sat, 13 Dec 2025 20:40:14 GMT access-control-allow-origin: * strict-transport-security: max-age=31556952 etag: W/"693dcf2e-c674" expires: Sun, 28 Dec 2025 08:07:38 GMT cache-control: max-age=600 content-encoding: gzip x-proxy-cache: MISS x-github-request-id: 7639:1387E:755EA2:839BDE:6950E2F1 accept-ranges: bytes age: 0 date: Sun, 28 Dec 2025 07:57:38 GMT via: 1.1 varnish x-served-by: cache-bom-vanm7210034-BOM x-cache: MISS x-cache-hits: 0 x-timer: S1766908659.502087,VS0,VE212 vary: Accept-Encoding x-fastly-request-id: 130017c20eb6eab54f9f26939ed65e2a1db32523 content-length: 8788 Efficient Processing of Neuro-Symbolic AI: A Software-Hardware Co-Design Tutorial

Efficient Processing of Neuro-Symbolic AI: A Cross-Layer Co-Design Tutorial

Students: Zishen Wan¹, Che-Kai Liu¹, Hanchen Yang¹, Ritik Raj¹, Jiayi Qian¹
Collaborators: Ananda Samajdar²
Principal Investigators: Arijit Raychowdhury¹, Tushar Krishna¹

¹Georgia Institute of Technology, ²IBM Research

Recent Talks

09/05/2025 "System Implications and Opportunities for Compositional Neuro-Symbolic-Probabilistic AI" at Georgia Tech (Host: Dr. Alexey Tumanov), Atlanta, GA.
07/11/2025 "Demystifying Neuro-Symbolic AI for Software-Hardware Co-Design" at Purdue University (Host: Dr. Anand Raghunathan), West Lafayette, IN.
07/10/2025 "Demystifying Neuro-Symbolic AI for Software-Hardware Co-Design" at University of Notre Dame (Host: Dr. Ningyuan Cao), South Bend, IN.
06/24/2025 "Tailored Computing: Domain-Specific Hardware and Systems for Embodied Cognitive Intelligence" at DAC PhD Forum, San Francisco, CA. [Slide]
06/24/2025 "NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI" at DAC, San Francisco, CA. [Slide]
06/21/2025 "Efficient and Safe Embodied Intelligence: From Benchmarking to Co-Design" at ISCA Arch4EAI Workshop, Tokyo, Japan. [Slide]
05/30/2025 "Efficient Processing of Neuro-Symbolic AI: A Tutorial and Co-Design Case Study" at NeuS, University of Pennsylvania, Philadelphia, PA.
05/11/2025 "Generative AI in Embodied Systems: System-Level Analysis of Performance, Efficiency and Scalability" at ISPASS, Ghent, Belgium. [Slide]
04/17/2025 "Demystifying Neuro-Symbolic AI for Software-Hardware Co-Design" at Google (Host: Dr. Suvinay Subramanian), Mountain View, CA. [Slide]
04/02/2025 "ReCA: Integrated Acceleration for Real-Time and Efficient Cooperative Embodied Autonomous Agents" at ASPLOS, Rotterdam, the Netherlands. [Slide]
03/31/2025 "Demystifying Neuro-Symbolic AI for Software-Hardware Co-Design" at ASPLOS MLBench Workshop, Rotterdam, the Netherlands. [Slide]
03/22/2025 "Bridging Learning and Reasoning: A Cross-Layer Software-Architecture-FPGA-SoC Approach for Neuro-Symbolic AI" at DARPA JUMP2.0 CoCoSys Annual Review, Atlanta, GA.
03/13/2025 "Programmable Silicon Prototyping for Various Neuro-Symbolic Models" at CoCoSys Industry Meeting, Atlanta, GA.
03/04/2025 "CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design AI" at HPCA, Las Vegas, NV. [Slide]
03/01/2025 "Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI" at HPCA MLBench Workshop, Las Vegas, NV. [Slide]
02/25/2025 "Tailored Computing: Domain-Specific Architecture for Embodied Cognitive Intelligence" at UIUC, Urbana-Champaign, IL. [Slide]
02/13/2025 "CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design AI" at CRNCH Summit, Atlanta, GA.
02/03/2025 "Tailored Computing: Domain-Specific Architecture for Embodied Cognitive Intelligence" at University of Washington (Host: Dr. Ang Li), Seattle, WA. [Slide]
01/28/2025 "Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI", at Georgia Tech (Host: Dr. Callie Hao), Atlanta, GA. [Slide]
01/24/2025 "Demystifying Neuro-Symbolic AI for Software-Hardware Co-Design" at Georgia Tech Computer Architecture Research Seminar, Atlanta, GA.
11/15/2024 "System-Architecture-Technology Cross-Layer Design for Embodied Intelligence" at Harvard University (Host: Dr. Gage Hills), Cambridge, MA.
11/07/2024 "Tailored Computing: Domain-Specific Architecture for Cognitive Intelligence" at University of Central Florida (Host: Dr. Di Wu), Orlando, FL. [Slide]
11/05/2024 "Efficient and Scalable Neurosymbolic System via Algorithm-Hardware Co-Design" at ACM Student Research Competition, MICRO, Austin, TX. [Slide]
11/03/2024 "Intelligence in Embodied Systems: Cross-Layer Co-Design for Intelligent Autonomous Machines" at MICRO RoboArch Workshop, Austin, TX. [Slide]
10/01/2024 "Neuro-Symbolic Architecture Meets Large Language Models: A Memory-Centric Perspective" at ESWEEK, Raleigh, NC. [Slide]
09/09/2024 "H3DFACT: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations" at SRC TECHCON, Austin, TX. [Slide]
08/15/2024 "Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI" at University of Minnesota, Minneapolis, MN. [Slide]
05/07/2024 "Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI" at ISPASS, Indianapolis, IN. [Slide]
04/27/2024 "Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI" at ASPLOS EMC2 Workshop, San Diego, CA. [Slide]
03/22/2024 "H3DFACT: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations" at DATE, Valencia, Spain. [Slide]

Abstract

Neuro-symbolic AI presents an emerging compositional paradigm that fuses neural learning with symbolic reasoning and probabilistic inference to enhance the transparency, interpretability, and trustworthiness of AI solutions for complex real-world tasks. However, achieving real-time, energy-efficient, and scalable deployment of neuro-symbolic intelligence requires cross-disciplinary integration through application discovery, systems thinking, and co-design intelligence.

We take a vertically-integrated approach to enabling efficient and scalable neuro-symbolic computing, from workload benchmarking, hardware architecture, to FPGA prototyping and SoC tapeout [NeuS'25]. First, we conduct workload characterization to uncover key system behavior of neuro-symbolic [ISPASS'24] and compositional LLM-symbolic-probabilistic [ASPLOS'26] models. Second, we perform system optimization and build processing elements and dataflow architecture for neuro-symbolic computing [HPCA'25] and compositional LLM-symbolic-probabilistic computing [HPCA'26]. Third, we develop end-to-end framework with automated architecture generator for agile neuro-symbolic FPGA deployment [DAC'25]. Finally, we tape out a programmable heterogeneous SoC chip with integrated RRAM/SRAM datapath, scheduler-informed power management, and programming support for neuro-symbolic AI models. Through this synergistic cross-layer co-design, we demonstrate the feasibility of deploying efficient neuro-symbolic cognitive systems at scale.

We also explore employing neuro-symbolic computing in embodied AI systems by integrating high-level planning-reasoning and low-level perception-control modules. Through system characterization [ISPASS'25] and development of dual memory system, hierarchical cooperation, and heterogeneous SoC architecture [ASPLOS'25], we aim to build more efficient and intelligent human-cognition-like physical AI systems that can better perceive, understand, reason, and interact with the complex real world.

Related Papers

Efficient Processing of Neuro-Symbolic AI: A Tutorial and Co-Design Case Study
Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Arijit Raychowdhury, Tushar Krishna
International Conference on Neuro-symbolic Systems (NeuS), 2025
Selected as Oral Presentation
Paper

This work presents our vertically integrated approach to enabling efficient and scalable neuro-symbolic computing—spanning workload benchmarking, hardware architecture, FPGA prototyping, and SoC tapeout. Through this cross-layer design, we demonstrate the feasibility of neuro-symbolic cognitive systems at scale.

Workload Characterization

Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI
Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Ananda Samajdar, Yingyan (Celine) Lin, Tushar Krishna, Arijit Raychowdhury
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2024
Best Poster Award, DARPA SRC JUMP2.0 CoCoSys Center 2024
Paper / Slide / Media

We systematically categorize neuro-symbolic AI workloads, conduct workload characterizations across hardware platforms, and identify cross-layer optimization opportunities for neuro-symbolic systems.

System Optimization

Compositional AI Beyond LLMs: System Implications of Neuro-Symbolic-Probabilistic Architectures
Zishen Wan, Hanchen Yang, Ritik Raj, Joongun Park, Chenyu Wang, Arijit Raychowdhury, Tushar Krishna
ACM Inter Conf on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2026
Best Paper Award, DARPA SRC JUMP 2.0, 2025
Paper

Compositional AI integrates LLMs, symbolic, and probabilistic modules to enhance interpretability, robustness, and trustworthiness for cognitive applications. This paper presents a comprehensive system-level analysis of neuro-symbolic-probabilistic AI and reveals its key performance characteristics.

Hardware Architecture

	REASON: Accelerating Probabilistic Logical Reasoning for Neuro-Symbolic Cognitive Intelligence Zishen Wan, Che-Kai Liu, Jiayi Qian, Hanchen Yang, Arijit Raychowdhury, Tushar Krishna IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2026 Paper (To appear) We propose REASON, an algorithm-system-architecture framework that accelerates the “slow-thinking” components of cognitive AI -- logical deduction, constraint solving, and probabilistic reasoning -- through common representation, reconfigurable architecture, and tight GPU integration for hybrid LLM + symbolic agentic workflows.
	CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design Zishen Wan, Hanchen Yang, Ritik Raj, Che-Kai Liu, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna International Symposium on High-Performance Computer Architecture (HPCA), 2025 Best Paper Award, DARPA SRC JUMP 2.0, 2024* Paper / Slide / Slide (long version) / Poster / Media We propose CogSys, a characterization and co-design framework dedicated to neurosymbolic AI system acceleration, aiming to win both reasoning efficiency and scalability.
	NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI Hanchen Yang, Zishen Wan, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna ACM/IEEE Design Automation Conference (DAC), 2025 Paper / Slide We propose NSFlow, an FPGA framework for efficient, scalable, and adaptive across neuro-symbolic systems. NSFlow features a design architecture generator that identifies workload data dependencies and creates dataflow architectures, as well as reconfigurable array with flexible compute units and re-organizable memory.
	Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Sixu Li, Youbin Kim, Ananda Samajdar, Yingyan (Celine) Lin, Mohamed Ibrahim, Jan M. Rabaey, Tushar Krishna, Arijit Raychowdhury IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI), 2024 Best Paper Award, DARPA SRC JUMP 2.0, 2024 Top-1 Most Cited Paper in all TCASAI Papers Paper / Fortune News / CoCoSys News We analyze the neuro-symbolic workload characteristics, and present a hardware acceleration case study for vector-symbolic architecture to improve the performance, efficiency, and scalability of neuro-symbolic computing.
	H3DFACT: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations Zishen Wan, Che-Kai Liu, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury Design, Automation and Test in Europe Conference (DATE), 2024 Best Presentation Award, SRC TECHCON 2024 Paper / Slide / SRC News / GT News We present H3DFACT, the first heterogeneous 3D integrated in-memory compute engine capable of efficiently factorizing high-dimensional holographic representations towards next-generative cognitive AI.
	Neuro-Symbolic Architecture Meets Large Language Models: A Memory-Centric Perspective Mohamed Ibrahim, Zishen Wan, Haitong Li, Priyadarshini Panda, Tushar Krishna, Pentti Kanerva, Yiran Chen, Arijit Raychowdhury ACM/IEEE Embedded Systems Week (ESWEEK), 2024 Paper / Slide We analyze the computational challenges of integrating LLMs and neuro-symbolic architecture, and explore state-of-the-art solutions, focusing on the memory-centric computing principles at both algorithmic and hardware levels.

Embodied System Deployment

ReCA: Integrated Acceleration for Real-Time and Efficient Cooperative Embodied Autonomous Agents
Zishen Wan, Yuhang Du, Mohamed Ibrahim, Jiayi Qian, Jason Jabbour, Yang (Katie) Zhao, Tushar Krishna, Arijit Raychowdhury, Vijay Janapa Reddi
ACM Inter Conf on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2025
Selected as Industry-Academia Partnership (IAP) Highlight
Best Paper Award, DARPA SRC JUMP 2.0, 2025
Paper / Slide / Slide (long version) / Poster / Media

We propose ReCA, a characterization and system-architecture co-design framework dedicated to cooperative embodied AI agent system acceleration, aiming to enhance both long-horizon multi-objective planning task efficiency and system scalability.

Generative AI in Embodied Systems: System-Level Analysis of Performance, Efficiency and Scalability
Zishen Wan, Jiayi Qian, Yuhang Du, Jason Jabbour, Yilun Du, Yang (Katie) Zhao, Arijit Raychowdhury, Tushar Krishna, Vijay Janapa Reddi
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2025
Paper / Slide

This paper systematically categorizes the workload characteristics of embodied agent systems and presents a benchmark suite to evaluate their task performance and system efficiency, and suggests system optimization strategies to improve the performance, efficiency, and scalability of future embodied system design.

Media Coverage

Georgia Tech News: Wan Wins First Place at Premier Computing Ph.D. Forum (07/2025)
Georgia Tech News: CoCoSys Develops Groundbreaking Neuro-Symbolic AI Chip (05/2025)
Fortune News: Generative AI can’t shake its reliability problem, some say ‘neurosymbolic AI’ is the answer (12/2024)
CoCoSys News: Research Scholar Spotlight from DARPA SRC JUMP2.0 Program (12/2024)

Acknowledgments

This work was supported in part by CoCoSys, one of seven centers in JUMP 2.0, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

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