Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
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Maximizing Coverage Metrics with Formal Unreachability Analysis | Synopsys
Maximizing Coverage Metrics with Formal Unreachability Analysis
Maximizing Coverage Metrics with Formal Unreachability Analysis
Coverage lies at the very heart of functional verification. Whether designing a single intellectual property (IP) block or a huge system on chip (SoC), verification teams need to know how well the design has been tested. Functional coverage, code coverage, toggle coverage, assertion coverage, and other metrics are widely used. Improving tests to fill in coverage holes is a key part of the process, but sometimes it seems that no progress is being made. This may be because some coverage targets are unreachable. This white paper describes how to detect unreachable coverage formally and what to do about it. The result of this methodology is better coverage and, therefore, a much greater chance of first-silicon success.