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Regzarr's Pastebin - Pastebin.com
| Name / Title | Added | Expires | Hits | Comments | Syntax | |
|---|---|---|---|---|---|---|
| SVV - Cucumber lab | Nov 26th, 2024 | Never | 253 | 0 | Java | - |
| LSIC - all labs so far in Verilog | Nov 25th, 2024 | Never | 934 | 0 | VeriLog | - |
| LSIC - Frequency Divider | Nov 25th, 2024 | Never | 877 | 0 | SystemVerilog | - |
| LSIC - 7 segment displays | Nov 25th, 2024 | Never | 950 | 0 | SystemVerilog | - |
| LSIC - Main System | Nov 25th, 2024 | Never | 903 | 0 | SystemVerilog | - |
| prj.tcl (LSIC lab) | Nov 19th, 2024 | Never | 113 | 0 | None | - |
| TimeMeasurement module (LSIC) | Nov 19th, 2024 | Never | 928 | 0 | VeriLog | - |
| cet_Test1_reqs | Nov 5th, 2024 | Never | 92 | 0 | None | - |
| DSP lab9 part2 | Apr 22nd, 2021 | Never | 1,163 | 0 | MatLab | - |
| CORDIC method | Dec 5th, 2019 | Never | 290 | 0 | C | - |
| frogs_lakes_WIP_Calin | Dec 4th, 2019 | Never | 316 | 0 | C | - |
| reg_file_16x32 | Nov 7th, 2019 | Never | 579 | 0 | VeriLog | - |
| bvd_to_e3_conv | Nov 7th, 2019 | Never | 620 | 0 | VeriLog | - |
| convo (needs fixing) | Jun 4th, 2019 | Never | 325 | 0 | C | - |
| first convolution v1.1 (notepad++ indentation) | Apr 15th, 2019 | Never | 336 | 0 | C | - |
| C Chess v0.12 | Mar 25th, 2019 | Never | 360 | 0 | C | - |
| sorting and searching | Mar 17th, 2019 | Never | 313 | 0 | C | - |
| unions, structs and bit fields | Mar 12th, 2019 | Never | 305 | 0 | C | - |
-
✅⭐ Make huge profits on trading ⭐⭐ 9
JavaScript | 1 min ago | 0.25 KB
-
⭐✅ Marketplace Glitch ✅ Working ✅ NEVER SEEN...
JavaScript | 1 min ago | 0.25 KB
-
⭐⭐⭐Make $1500 in 20 minutes⭐⭐
Java | 1 min ago | 0.10 KB
-
⭐✅ Exploit 2500$ in 15 Minutes⭐⭐⭐ 8
JavaScript | 1 min ago | 0.25 KB
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Free Crypto Method (NEVER SEEN BEFORE)⭐⭐ O
JavaScript | 1 min ago | 0.25 KB
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⭐⭐⭐Exploit 500$ in 15 Minutes⭐⭐
Java | 1 min ago | 0.10 KB
-
⭐✅ Swapzone Glitch ✅ Working ⭐⭐ 9
JavaScript | 2 min ago | 0.25 KB
-
⭐⭐⭐Profit Method⭐⭐
Java | 2 min ago | 0.10 KB
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