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module moore_fsm( output reg parity, input clk, input reset, - Pastebin.com
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- module moore_fsm(
- output reg parity,
- input clk,
- input reset,
- input x);
- reg state, next_state;
- parameter S0=0;
- parameter S1=1;
- // Partea secvențială
- always @(posedge clk or negedge reset)
- if (!reset)
- state <= S0;
- else
- state <= next_state;
- always @(*) begin
- case(state)
- S0: begin
- parity = 0;
- if (x)
- next_state = S1;
- else
- next_state = S0;
- end
- S1: begin
- parity = 1;
- if(!x)
- next_state = S1;
- else
- next_state = S0;
- end
- endcase
- end
- endmodule
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