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package vexriscv.demoimport spinal.core._import spinal.lib._import spi - Pastebin.com
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- package vexriscv.demo
- import spinal.core._
- import spinal.lib._
- import spinal.lib.bus.amba3.apb._
- import spinal.lib.bus.amba4.axi._
- import spinal.lib.io.{TriStateArray, TriState}
- import spinal.lib.misc.HexTools
- import scala.collection.mutable.ArrayBuffer
- import scala.collection.Seq
- case class USB23_IO() extends Bundle with IMasterSlave {
- val VBUS = Analog(Bits(1 bits))
- val DM = Analog(Bits(1 bits))
- val DP = Analog(Bits(1 bits))
- val REFINCLKEXTP = Analog(Bits(1 bits))
- val REFINCLKEXTM = Analog(Bits(1 bits))
- val RESEXTUSB2 = Analog(Bits(1 bits))
- val RXP = Analog(Bits(1 bits))
- val RXM = Analog(Bits(1 bits))
- val TXP = Analog(Bits(1 bits))
- val TXM = Analog(Bits(1 bits))
- val clkIn = Bool
- val dOut = Bool
- override def asMaster() : Unit = {
- out(dOut)
- in(clkIn)
- inout(VBUS, DM, DP, REFINCLKEXTM, REFINCLKEXTP, RESEXTUSB2, RXM, RXP,
- TXM, TXP)
- }
- }
- case class USB23() extends BlackBox {
- val io = new Bundle {
- val clkIn = in Bool()
- val io = master(USB23_IO())
- }
- noIoPrefix()
- }
- class TinyClunx(
- onChipRamSize : BigInt
- ) extends Component{
- val axiMConfig = Axi4Config(
- addressWidth = 17,
- dataWidth = 64,
- idWidth = 3,
- useRegion = false,
- useLock = false,
- useQos = false,
- useResp = false,
- useProt=false,
- useStrb=false
- )
- val axiSConfig = Axi4Config(
- addressWidth = 17,
- dataWidth = 64,
- idWidth = 4,
- useRegion = false,
- useLock = false,
- useQos = false,
- useResp = false,
- useProt=false,
- useStrb=false
- )
- val io = new Bundle{
- //Clocks / reset
- val axiReset = in Bool()
- val axiClk = in Bool()
- val axiM1 = slave(Axi4(axiMConfig))
- //val usbIO = master(USB23_IO())
- val axiM2 = slave(Axi4Shared(axiMConfig))
- val axiS1 = master(Axi4Shared(axiSConfig))
- }
- noIoPrefix()
- val axiClockDomain = ClockDomain(
- clock = io.axiClk,
- reset = io.axiReset
- )
- val axi1 = new ClockingArea(axiClockDomain) {
- val ram1 = Axi4SharedOnChipRam(
- dataWidth = 64,
- byteCount = onChipRamSize,
- idWidth = axiMConfig.idWidth+1
- )
- /*
- val ram2 = Axi4SharedOnChipRam(
- dataWidth = 64,
- byteCount = onChipRamSize,
- idWidth = axiConfig.idWidth+1
- )
- */
- //val axiM2 = Axi4(axiConfig)
- //val usbCore = new USB23
- val axiCrossbar = Axi4CrossbarFactory()
- axiCrossbar.addSlaves(
- ram1.io.axi -> (0x00000000L, onChipRamSize),
- io.axiS1 -> (0x00010000L, onChipRamSize)
- )
- axiCrossbar.addConnections(
- io.axiM2 -> List(ram1.io.axi, io.axiS1),
- io.axiM1 -> List(ram1.io.axi, io.axiS1)
- )
- axiCrossbar.build()
- }
- //usbCore.io.clkIn := io.axiClk
- //io.usbIO := usbCore.io.io
- }
- object TinyClunx{
- def main(args: Array[String]) {
- val config = SpinalConfig()
- config.generateVerilog({
- val toplevel = new TinyClunx(onChipRamSize = 8 kB)
- toplevel
- })
- }
- }
- // With memory init
- object TinyCClunxWithMemoryInit{
- def main(args: Array[String]) {
- val config = SpinalConfig()
- config.generateVerilog({
- val toplevel = new TinyClunx(onChipRamSize = 8 kB)
- HexTools.initRam(toplevel.axi1.ram1.ram, "src/main/ressource/hex/muraxDemo.hex", 0x80000000l)
- toplevel
- })
- }
- }
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