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;; vga_test.asm;; Created: 2/20/2016 6:44:02 PM; Author : jimlkosmo; - Pastebin.com
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- ;
- ; vga_test.asm
- ;
- ; Created: 2/20/2016 6:44:02 PM
- ; Author : jimlkosmo
- ;
- .org 0
- rjmp RESET ;reset
- .org OC1Aaddr
- rjmp TIM1_COMPA ;isr for tc1 Compare Match A
- .org OC1Baddr
- rjmp TIM1_COMPB ;isr for tc1 Compare Match B
- RESET:
- sbi ddrb,4 ; HORIZONTAL SYNC PULSE
- sbi ddrb,3 ;red
- sbi ddrb,2 ;green
- sbi ddrb,0 ;blue
- sbi ddrb,1 ; VERTICAL SYNC PULSE
- ldi r16,(1<<PORTB4); H_SYNC PIN HIGH
- out PORTB,r16
- in r16,PORTB; V_SYNC PIN LOW
- sbr r16,(0<<PORTB1)
- out PORTB,r16
- ;stack_pointer
- ldi r16,ramend
- out spl,r16
- ;setup interrupts
- clr r16
- ldi r16,(1<<COM1B0); Toggle in OC1B when Comp Match on OCR1B
- out TCCR1A,r16
- ldi r16,(1<<CS10 | 1<<WGM12) ;CTC on OCR1A Comp Match and set CLKin
- out TCCR1B,r16
- ldi r16,(1<<OCIE1A | 1<<OCIE1B) ;TC1 Output Comp Match Interrupt Enabled on A and B channel
- out timsk,r16
- ldi r16,high(635); Load Max for TC1
- out ocr1ah,r16
- ldi r16,low(635)
- out ocr1al,r16
- ldi r16,0
- out tcnt1h,r16; clear tc1
- out tcnt1l,r16
- ldi r16,high(12); Load first toggle value for H_SYNC (13 clock pulses)
- out ocr1bh,r16
- ldi r16,low(12)
- out ocr1bl,r16
- ldi r16,0
- out tcnt1h,r16; clear tc1
- out tcnt1l,r16
- ldi r18,10; Load r18 with the first value of vsync toggle
- ldi r19,44 ;[1] load r19 with the value of the first visible line
- ldi r20,0 ;[1]
- ldi r21,low(126); load r21,r22 with the value of the first visible pixel
- ldi r22,high(126)
- clr r28
- clr r29
- clr r16
- sei; interrupts globally enabled
- main:
- cp r28,r19 ;[1]
- cpc r29,r20 ;[1]
- brlo no_vid ;[1/2] Are we in vertical visible area?
- in r26,tcnt1l;
- in r27,tcnt1h
- cp r26,r21 ;[1]
- cpc r24,r22 ;[1]
- brlo no_vid ;[1/2] Are we in horizontal visible area?
- in r16,PORTB; white space
- sbr r16,(1<<PORTB0)|(1<<PORTB2)|(1<<PORTB3)
- out PORTB,r16
- rjmp main
- no_vid:
- in r16,PORTB; black space
- sbr r16,(0<<PORTB0)|(0<<PORTB2)|(0<<PORTB3)
- out PORTB,r16
- rjmp main
- TIM1_COMPA:
- in r16,sreg ; SAVE STATUS REGISTER [1]
- push r16;[2]
- ldi r16,low(12); Load first toggle value for H_SYNC (13 clock pulses) [1]
- ldi r17,high(12);
- out ocr1bh,r17;[2]
- out ocr1bl,r16
- adiw r29:r28,1 ;[2] V_SYNC counter++
- ldi r17,0 ;[1]
- cp r18,r28 ;[1]
- cpc r17,r29 ;[1]
- breq vsync_toggle ;[1/2] If we got 10 or 12 lines
- ldi r16,low(525) ;[1]
- ldi r17,high(525) ;[1]
- cp r16,r28 ;[1]
- cpc r17,r29 ;[1]
- breq cls_vsync ;[1/2] If we got 525 lines
- cont:
- pop r16 ;[2] RESTORE sreg
- out sreg,r16 ;1
- reti ;[4] return operation to software
- TIM1_COMPB:
- in r16,sreg ; SAVE STATUS REGISTER [1]
- push r16;[2]
- ldi r16,low(87); Load second toggle value for H_SYNC (13+76 clock pulses)
- out ocr1bl,r16
- pop r16 ;[2] RESTORE sreg
- out sreg,r16 ;1
- reti ;[4] return operation to software
- vsync_toggle:
- sbi PINB,1;toggle v_sync
- ldi r18,12 ;set r18 with 12
- rjmp cont
- cls_vsync:
- ldi r18,10 ;set r18 with 10
- ldi r28,0; reset v_sync counter
- ldi r29,0
- rjmp cont
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