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ARM_RAMB_4kx32 - Pastebin.com
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- --------------------------------------------------------------------------------
- -- Wrapper um Basys3-Blockram fuer den RAM des HWPR-Prozessors.
- --------------------------------------------------------------------------------
- -- Datum: 23.05.2022
- -- Version: 1.1
- --------------------------------------------------------------------------------
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- entity ArmRAMB_4kx32 is
- generic(
- --------------------------------------------------------------------------------
- -- SELECT_LINES ist fuer das HWPR irrelevant, wird aber in einer
- -- komplexeren Variante dieses Speichers zur Groessenauswahl
- -- benoetigt. Im Hardwarepraktikum bitte ignorieren und nicht aendern.
- --------------------------------------------------------------------------------
- SELECT_LINES : natural range 0 to 2 := 1);
- port(
- RAM_CLK : in std_logic;
- ENA : in std_logic;
- ADDRA : in std_logic_vector(11 downto 0);
- WEB : in std_logic_vector(3 downto 0);
- ENB : in std_logic;
- ADDRB : in std_logic_vector(11 downto 0);
- DIB : in std_logic_vector(31 downto 0);
- DOA : out std_logic_vector(31 downto 0);
- DOB : out std_logic_vector(31 downto 0));
- end entity ArmRAMB_4kx32;
- architecture behavioral of ArmRAMB_4kx32 is
- type ram_type is array (4095 downto 0) of std_logic_vector(31 downto 0);
- signal RAM : ram_type;
- begin
- WRITE_AND_READ: process(RAM_CLK)
- begin
- if(rising_edge(RAM_CLK)) then
- if (ENA = '1') then --wenn enable A, lesen aus dem RAM anstelle (int) der entsprechenden Register Adresse
- DOA <= RAM(to_integer(unsigned(ADDRA)));
- end if;
- -- DIB hat die Form: |++++|++++|++++|++++| besteht aus 32 Bit - 4 Bloecken
- if (ENB = '1') then --wenn enable B, kann man aus B lesen oder auf B schreiben, je nach WEB
- if (WEB = "0000") then --lesezugriff auf port B
- DOB <= RAM(to_integer(unsigned(ADDRB)));
- end if;
- if (WEB(0) = '1') then --erstes block (die letzten 8Bit) schreiben
- RAM(to_integer(unsigned(ADDRB)))(7 downto 0) <= DIB(7 downto 0);
- end if;
- if (WEB(1) = '1') then -- zweites block
- RAM(to_integer(unsigned(ADDRB)))(15 downto 8) <= DIB(15 downto 8);
- end if;
- if (WEB(2) = '1') then --drittes block
- RAM(to_integer(unsigned(ADDRB)))(23 downto 16) <= DIB(23 downto 16);
- end if;
- if (WEB(3) = '1') then --viertes block
- RAM(to_integer(unsigned(ADDRB)))(31 downto 24) <= DIB(31 downto 24);
- end if;
- end if;
- end if;
- end process;
- end architecture behavioral;
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