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1. sky130_schematics sky130_schematics Public

   Verified visual schematics for all SKY130 Cells

   Tcl 10 13

2. vivado_acorn vivado_acorn Public

   An example repo showing how to get started with the Lite/NiteFury(II) and Sqrl Acorn 101/215(+) FPGAs

   Tcl 6

3. verilog_template verilog_template Public template

   This project demonstrates a scalable format for Verilog including build scripts, design verification, and synthesis.

   Tcl 4 3

4. xschem_3d xschem_3d Public

   This project aims to create visual representations of voltage propogating through analog circuits. It uses Ngspice, Xschem, and Blender.

   Python 1

5. labs-with-cva6 labs-with-cva6 Public

   Advanced Architecture Labs with CVA6

   SystemVerilog 68 27

6. thesis thesis Public

   Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

   TeX 4 1