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This crate is guaranteed to compile on current stable Rust.
It might compile with older versions but that may change in any new patch release.
Usage
Please note that for using this crate's register definitions (as provided by
aarch64_cpu::registers::*), you need to also import
aarch64_cpu::registers::{Readable, Writeable}.
use aarch64_cpu::{asm, registers::*};// Some parts omitted for brevity.unsafefnprepare_el2_to_el1_transition(virt_boot_core_stack_end_exclusive_addr:u64,virt_kernel_init_addr:u64,){// Enable timer counter registers for EL1.CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);// No offset for reading the counters.CNTVOFF_EL2.set(0);// Set EL1 execution state to AArch64.HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64);// Set up a simulated exception return.SPSR_EL2.write(SPSR_EL2::D::Masked
+ SPSR_EL2::A::Masked
+ SPSR_EL2::I::Masked
+ SPSR_EL2::F::Masked
+ SPSR_EL2::M::EL1h,);}
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the
work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any
additional terms or conditions.
Code of Conduct
Contribution to this crate is organized under the terms of the Rust Code of
Conduct, the maintainer of this crate, the Cortex-A team, promises
to intervene to uphold that code of conduct.
About
Low level access to processors using the AArch64 execution state.