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Releases: riscvarchive/riscv-code-size-reduction
v1.0.4-3 add misa.C clarification
786f510
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Add section defining when to set misa.C
Assets 3
v1.0.4-2
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Add rule that C implies Zca, C+F also implies Zcf (RV32), C+D also implies Zcd
Assets 3
v1.0.4-1
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Clarification that Zcf implies F and Zcd implies D
Clarification that Zcf is RV32 only
Assets 3
v1.0
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This release was created by: rpsene
This extension is Ratified. No changes are allowed. Any desired or needed changes can be the subject of a follow-on new extension. Ratified extensions are never revised. See https://riscv.org/spec-state.
Zc* is a group of extensions which define subsets of the existing C extension (Zca, Zcd, Zcf) and new extensions which only contain 16-bit encodings.
Zcm* all reuse the encodings for c.fld, c.fsd, c.fldsp, c.fsdsp.
Assets 3
Non-normative clarification regarding non-idempotent memory
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v1.0.3-1 v1.0.3-1 non-normative non-idempotent memory clarification
Assets 3
v1.0.3 add defintion of Zce
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v1.0.3 add definition of Zce
Assets 3
v1.0.2-1 ratification ready
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make register field names consistent for c.mul, c.not, c.zext.b
Assets 3
v1.0.2 ratification ready
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Updated instruction formats following Architecture Review Committee feedback
Assets 3
v1.0.1 Post public review fixes
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v1.0.1 - post public review fixes
Assets 3
PUBLIC REVIEW REVISION v1.0.0-RC5.7
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public review revision, v1.0.0-RC5.7 (more consistent version number)