CV32A60X configuration release for TRL5
This release contains only this specific configuration.

What's Changed (Major changes)

With respect to CV32A60X available in v5.3.0 release

• Create pipeline hierarchy with OBI as interface
• No caches
• No PMP entries
• Disable Zifencei
• Improve code coverage
• Improve functional coverage
• Improve lint results
• Docs: add CV32A60X configuration in RISC-V ISA manual
• Docs: add CV32A60X design document

Full Changelog: v5.3.0...cv32a60x-v6.0.0

What's Changed (Major changes)

• Support of Zcmt
• Support of Zcmp, Zcmt and CV-X-IF with superscalar

Full Changelog: v5.2.0...v5.3.0

What's Changed (Major changes)

• Support of CV-X-IF 1.0.0
• Support of Zbkb
• Support of superscalar
• Support of Altera FPGA
• PMP independent from MMU
• Spike tandem for verification
• LLVM toolchain build scripts

Full Changelog: v5.1.0...v5.2.0

What's Changed (major changes)

• Hypervisor extension
• MMU refactoring (unified with H extension)
• Use cv32a6_imac_sv32 to generate FPGA bitstream
• New target with MMU: cv64a6_mmu
• SpyGlass lint in CI
• RISC-V ISA manual for CV32A65X

Full Changelog: v5.0.0...v5.1.0

Assets

• ariane_xilinx_cv32a6_imac_sv32.bit: 32-bit configuration

What's Changed

• Fix cv64a6 configurations

Assets

• ariane_xilinx_cv32a60x.bit: 32-bit configuration

This is the first release of a new series.

What's Changed

Too many changes since previous release to be reported here.

Full Changelog: v4.2.0...v5.0.0

Assets

• ariane_xilinx_cv32a60x.bit: 32-bit configuration

Added

• Check execute PMA on instruction frontend
• Add support for non-contiguous cacheable regions to the PMA checks
• Provision exponential backoff for AMO SC in L1 D$ miss handler

Changed

• Several small fixes to get the code running on VCS
• Fix compressed instruction decoding in tracer
• Fix privilege bug in performance counters. The counters have always been accessible in user mode.
• Fix RISC-V PK simulation bug caused due to insufficient time to init the a0 and a1 registers via the bootrom
• Fix bug in wt_axi_adapter (only appeared when dcache lines were wider than icache lines)
• Fix potentially long timing path in axi_lite_interface
• Fix VCS elab warning in load_store_unit
• Replace PLIC with implementation from lowRISC
• Re-work interrupt and debug subsystem to associate requests during decode. This improves stability on for non-idempotent loads.
• Bump fpnew to v0.5.5
• Bump axi to v0.7.0
• Bump common_cells to v1.13.1
• Bump riscv-dbg to v0.1
• Improve FPU pipelining and timing around scoreboard
• Reworked the axilite to PLIC shim for OpenPiton+Ariane
• Remove in and out aliases for AXI interfaces
• Fix small issues with DC synthesis
• Fix wrong dirtying of sd flag in mstatus
• Synthesis fix for Vivado 2018.3
• Clean-up instruction front-end, small IPC improvement
• Move to Verilator 4.014

Added

• Official support for floating point unit
• Added AXI-64bit adapter for write-through cache system
• Added AXI atomic ops and exclusive access support to write-through cache system
• Provision riscv-isa-sim tandem simulation
• Support for preloading

Changed

• Rerouted the JTAG from PMOD to the second channel of FTDI 2232 chip on Genesys 2 board
• Increase available RAM size on Genesys II board to 1 GiB
• Fixed problem which decoded compressed hints as illegal instructions
• Bugfixes in write-through cache system
• ID width fix in random delayer

4.0.0

Added

• Preliminary support for A-Extension
• Preliminary FP support
• Preliminary support for OpenPiton cache system
• Commit log feature
• Provisioned aw_top signal for close to memory atomics
• FPGA Support
• Misc bug-fixes
• Platform Level Interrupt Controller (PLIC)
• FPGA Bootrom with capability to boot from SD Card

Changed

• core_id / cluster_id inputs have been merged to hard_id input (interface changes)
• The three AXI ports have been merged into one (interface changes)
• [Bugfix] Wrong flagging of memory in machine mode if high bits (63-38) are not equal #136