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Further optimize fastDepthwiseConv for RISC-V Vector. by hanliutong Β· Pull Request #25361 Β· opencv/opencv Β· GitHub
hanliutong
changed the title
Further optimize fastDepthwiseConv for RVV.
Further optimize fastDepthwiseConv for RISC-V Vector.
Apr 7, 2024
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Further optimize fastDepthwiseConv for RISC-V Vector. #25361
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mshabunin
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This patch optimize
fastDepthwiseConv
in the f32 layer by using RVV Native Intrinsic.This patch was tested on QEMU using VLEN=128 and VLEN=256 (
./bin/opencv_test_dnn
), both GCC (trunk) and Clang (16.0.6) are passed;On the real device (k230, VLEN=128, Clang 16.0.6), For valid test cases in
conv::Conv_Depthwise
,opencv_perf_dnn
showed the average acceleration of5.74x
for strided cases (benefit from using stride load instead of buffer) and1.55x
for non-strided cases (benefit from using more vector registers, m2 -> m8).Test Result ( in descending order of acceleration ratio)
Pull Request Readiness Checklist
See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request
Patch to opencv_extra has the same branch name.