(setq verilog-ext-tags-backend 'tree-sitter)

(setq verilog-ext-project-alist
      `(("ucontroller"
         :root "/home/gonz/Repos/larumbe/ucontroller"
         :files ("src/pkg/global_pkg.sv"
                 "src/alu/rtl/alu.sv"
                 "src/misc/rtl/bin2bcd.sv"
                 "src/cpu/rtl/cpu.sv"
                 "src/dma/rtl/dma.sv"
                 "src/dma/rtl/dma_arbiter.sv"
                 "src/dma/rtl/dma_rx.sv"
                 "src/dma/rtl/dma_tx.sv"
                 "src/uart/rtl/fifo_wrapper.sv"
                 "src/ram/rtl/gp_ram.sv"
                 "src/ram/rtl/ram.sv"
                 "src/top/rtl/ram_arbiter.sv"
                 "src/ram/rtl/regs_ram.sv"
                 "src/uart/rtl/sreg.sv"
                 "src/uart/rtl/uart.sv"
                 "src/uart/rtl/uart_rx.sv"
                 "src/uart/rtl/uart_tx.sv"
                 "src/top/rtl/ucontroller.sv"
                 "src/uart/tb/fifo_generator_0_sim_netlist.v"
                 "src/top/tb/tb_clocks.sv"
                 "src/top/tb/tb_program.sv"
                 "src/top/tb/tb_top.sv"
                 "src/dma/tb/tb_dma.sv"
                 "src/alu/tb/tb_alu.sv"
                 "src/misc/tb/tb_bin2bcd.sv"
                 "src/cpu/tb/tb_cpu.sv"
                 "src/ram/tb/tb_ram.sv"
                 "src/uart/tb/tb_uart.sv")
         :ignore-files ("src/uart/tb/fifo_generator_0_sim_netlist.v")
         :compile-cmd "make tb_top" ; command used to compile current project
         ;; `vhier' related properties
         :command-file "commands.f" ; vhier command file
         :lib-search-path nil)))    ; list of dirs to look for include directories or libraries