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Release v0.11.0-esp32-20220706 · espressif/openocd-esp32 · GitHub
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v0.11.0-esp32-20220706
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2008 commits
to master
since this release
2022/07/06 Release, based on OpenOCD v0.11.0
Features:
- esp32c2: Adds generic support for ESP32-C2.
- esp32c3: Implements logging the reason of the reset. The reason is printed in numerical and human readable format.
- espxx: Implements
soft_reset_halt
command. - esp/semihosting: Adds full support for ESP IDF VFS driver directory API.
- esp/flash: Adds
no_clock_boost
argument toprogram_esp
andprogram_esp_bins
commands. This can be helpful when users experience problems with flash programming. It forbids OpenOCD to modify (boost) CPU clock in order to speed up flashing. - freertos: Adds support for
qGetTLSAddr
GDB packet. This fixes problem appeared on Xtensa targets when user tried to print TLS variable value in GDB. - freertos: Enables reading some Xtensa registers for waiting tasks (e.g. threadptr). Zero values were returned before this change.
- freertos: Support Amazon FreeRTOS SMP port (available in IDF starting from IDF 5.0)
- doc: Updates description of Espressif-specific commands.
Bug fixes:
- esp32s3: call
smp_target_init
instead of single core init. - rtos/esp32: Fixed
AddressSanitizer
heap-buffer-overflow issue when reading registers from ESP32 stack. - xtensa: Invalidates register cache on reset. This could lead to writing to target old registers values after chip reset and could lead to unpredictable behavior.
- esp/flash: Fixed memory leaks in ESP flash driver reported by valgrind.
Other:
- Synchronized with upstream changes
- Refactored for upstreaming patches
Assets 9
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