Features

• [chiselsim] Stop using CIRCT filelists (by @seldridge in #4969)
• [chiselsim] Use allowlist for compilation includes (by @seldridge in #4970)

Dependency Updates

• [cd] Bump CIRCT from firtool-1.124.0 to firtool-1.125.0 (by @chiselbot in #4973)
• [cd] Bump CIRCT from firtool-1.124.0 to firtool-1.125.0 (by @chiselbot in #4974)

Build and Internal Changes

• [Scala3] Split plugin resource files based on Scala major version (by @adkian-sifive in #4971)
  Split plugin resource files into separate directories for Scala 2 and Scala 3
• [Scala3] Add Bundle plugin (by @adkian-sifive in #4947)
  Adds Bundle plugin
• Upgrade to Mill 1.0.0 (by @jackkoenig in #4972)
  No SNAPSHOT publishing yet, that will be follow on work. See the Mill 1.0.0 changelog.

Full Changelog: v7.0.0-RC2...v7.0.0-RC3

Features

• [core] Add Bool "implies" method (by @seldridge in #4933)
• Add timing parameter support to Verilator backend (by @shahzaibk23 in #4934)
  Added extra option Verilator Backend for Timing option. User now has choice to either add --timing or --no-timing or nothing for this parameter, in the Verilator Args Seq
• [svsim] Trace options for the Verilator backend (by @kammoh in #4911)
• [chiselsim] Add Randomization.x (by @seldridge in #4939)
• Allow bare Chisel types to be looked up from a Hierarchy (by @tmckay-sifive in #4940)
  • Allow lookup of bare Chisel types from a Hierarchy
• [chiselsim] Add frequency control to stimulus (by @seldridge in #4942)
• Add API to include comments in the FIRRTL (by @jackkoenig in #4949)
  This is for debugging generated FIRRTL only--comments are ignored by the FIRRTL compiler.
• Add Lookupable for ActualDirection (by @tmckay-sifive in #4950)
  • Allow ActualDirection to be looked up from a Hierarchy
• ChiselSim API for inline testing (by @tmckay-sifive in #4946)
  • Add a ChiselSim API for simulating inline tests
• Add OverrideSerializationClass for custom annotation serialization (by @jackkoenig in #4953)
  Annotations can now mixin OverrideSerializationClass to customize the "class" field in annotation serialization. This allows annotation classes to reside in a different package than firtool is expecting for the class field. Note that this breaks automatic deserialization which does not matter to firtool but would matter for annotations communicating information between Chisel generator invocations.
• ChiselSim peek/poke/expect for Enums, Records, Vecs, and generic Data (by @kammoh in #4824)

API Modification

• Support concatenating Properties of Seq subtypes (by @debs-sifive in #4907)
• Fail boring into module with endIOCreation set (by @azidar in #4925)
  Setting endIOCreation now also errors if any IOs are created using BoringUtils.

Fixes

• Improve error for bad connections with null module name (by @jackkoenig in #4917)
• [testing] Mangle more directories (by @seldridge in #4927)
• [testing] Mangle even more directories (by @kammoh in #4928)
• [svsim/ChiselSim] Discover the project's root directory in a sandboxed build (by @kammoh in #4931)
• Fix naming plugin support for unapply (by @jackkoenig in #4943)
  Previously, naming support on unapply only worked for subtypes of Data, but now it works for all namable types, including user-extensible AffectsChiselName as well as non-Data Chisel built-in types: Mem, VerificationStatement, properties.DynamicObject, and Disable.

Documentation

• Table on Java version (by @schoeberl in #4909)
• [blog] Add blog post about Latch Up 2025 (by @jackkoenig in #4914)
• fix: queue depth parameter name (by @edwardcwang in #4922)
• [docs] Fix RawClockedVoidFunctionCall example (by @yizishun in #4937)
• [docs] Fix BlackBoxRealAdd port widths (by @tymcauley in #4957)

Dependency Updates

• [cd] Bump CIRCT from firtool-1.114.1 to firtool-1.115.0 (by @chiselbot in #4908)
• [cd] Bump CIRCT from firtool-1.115.0 to firtool-1.116.0 (by @chiselbot in #4912)
• [cd] Bump CIRCT from firtool-1.116.0 to firtool-1.117.0 (by @chiselbot in #4920)
• [cd] Bump CIRCT from firtool-1.117.0 to firtool-1.118.0 (by @chiselbot in #4926)
• [cd] Bump CIRCT from firtool-1.118.0 to firtool-1.119.0 (by @chiselbot in #4936)
• [cd] Bump CIRCT from firtool-1.119.0 to firtool-1.120.0 (by @chiselbot in #4944)
• [cd] Bump CIRCT from firtool-1.120.0 to firtool-1.121.0 (by @chiselbot in #4948)
• [cd] Bump CIRCT from firtool-1.121.0 to firtool-1.122.0 (by @chiselbot in #4954)
• [cd] Bump CIRCT from firtool-1.122.0 to firtool-1.123.0 (by @chiselbot in #4960)
• [cd] Bump CIRCT from firtool-1.123.0 to firtool-1.123.1 (by @chiselbot in #4962)
• [cd] Bump CIRCT from firtool-1.123.1 to firtool-1.123.2 (by @chiselbot in #4965)
• [cd] Bump CIRCT from firtool-1.123.2 to firtool-1.124.0 (by @chiselbot in #4966)
• Bump os-lib to 0.10.7 (by @jackkoenig in #4967)
  Also bump mdoc to 2.7.1 (but this isn't visible to users).
  Note that we are not yet bumping os-lib to 0.11 because it will raise the minimum supported JVM to 11. Similarly we are not bumping upickle to 4.0 because it does not support Scala 3.3 which is our target for Scala 3 support (because 3.3 is LTS).

Build and Internal Changes

• Revert "build: bump to mill 0.12.10" (by @unlsycn in #4906)
• [chiselsim] Set +incdir on all primary sources (by @seldridge in #4923)
• Update Mill to 0.12.14 (by @jackkoenig in #4961)

Full Changelog: v7.0.0-RC1...v7.0.0-RC2

Features

• Add AffectsChiselName (by @adkian-sifive in #4283)
  Adds new trait AffectsChiselName that adds support for naming user-defined types
• Add --remap-layers to ChiselStage (by @seldridge in #4322)
• Add common layers to Chisel (by @seldridge in #4326)
• Add skipIfAlreadyInBlock arg to layer.block (by @seldridge in #4327)
• Add skipIfLayersEnabled param to layer.block (by @seldridge in #4346)
• Add layer.elideBlocks API (by @seldridge in #4348)
• Make layer.addLayer API public (by @seldridge in #4349)
• Add Property expression for list concatenation. (by @mikeurbach in #4347)
  This adds a list concatenation operation for Property[Seq[T]], using the same typeclass approach used for other Property expressions.
• Add support for circt.OutputDirAnnotation. (by @dtzSiFive in #4352)
  Expose capability to request a Module be placed in a specific directory.
  Functions as with Layer output directories.
• Make '--module' support arguments (by @seldridge in #4358)
• Add DataMirror API for currentInstancePorts. (by @mikeurbach in #4362)
  This allows users to query an Instance without it being closed or forcing it to close, which can be useful in atModuleBodyEnd and other scenarios.
• Add experimental Select APIs for current instances in a BaseModule. (by @mikeurbach in #4363)
  This is useful in situations like atModuleBodyEnd to reflect on the current BaseModule before it is closed.
• Add Path.apply() to support HasTarget (by @debs-sifive in #4364)
  Adds Path.apply() function that support HasTargets, so that the paths of things that extend HasTarget, like SRAM, can be put into properties.
• feat: implement SerializableModuleElaborator (by @unlsycn in #4409)
  Add SerializableModuleElaborator
• Add SourceLocator for Sequence (by @unlsycn in #4436)
  Add source locator for Sequence
• Add Property expression for integer shift left (by @maerhart in #4440)
  This adds an API for integer Property shift left.
• Support creation of Paths from HasTargets (by @debs-sifive in #4455)
• Add --firtool-option arg to ChiselStage (by @seldridge in #4463)
• switch SRAMDescription to Class (by @sequencer in #4437)
• add additionalAnnotations for SerializableModuleElaborator (by @sequencer in #4477)
• Implement Lookupable for HasTarget (used by SRAM) (by @jackkoenig in #4481)
• Allow BoringUtils to use existing port in a closed module (by @tmckay-sifive in #4484)
  When trying to drill a port, it doesn't matter if the module is closed. We do not need to construct new hardware and can just use the existing port.
• Implement Lookupable for Unit (by @jackkoenig in #4497)
• [Module] Add afterModuleBuilt hook (by @fabianschuiki in #4479)
  The new afterModuleBuilt hook can be used to schedule code to be executed once a module has been fully generated and its definition is available. This allows further collateral such as unit tests to be generated alongside a module.
• Add withModulePrefix (by @mmaloney-sf in #4487)
• Add AutoBlackbox (by @unlsycn in #4495)
• Add new InlineInstanceAllowDedup trait (by @rwy7 in #4508)
• Add module prefixing to BaseModule definitions (by @jackkoenig in #4509)
  • BaseModule.localModulePrefix can be used to set a prefix for the module and its children.
  • BaseModule.localPrefixAppliesToSelf (defaults to true) allows the module to exclude itself from the prefix.
  • localModulePrefix composes with prefixes added via withModulePrefix.
• feat: add CIRCTSRAMInterface (by @unlsycn in #4494)
  Add CIRCTSRAMInterface
• Add APIs to omit module prefix separator (by @jackkoenig in #4532)
  • withModulePrefix now optionally takes a 2nd parameter includeSeparator (passing false will omit separator).
  • Overriding localModulePrefixUseSeparator in a Module to false will omit separator for local prefix applied by overriding localModulePrefix in that Module.
• feat: add SRAMBlackBox (by @unlsycn in #4544)
• Add partial cross-compilation for Scala 3 (by @adkian-sifive in #4549)
  Adds initial support for Scala 3 LTS version 3.3.3
• [util] Add a withShadowLayer Queue (by @seldridge in #4589)
• Add FormalTest marker (by @fabianschuiki in #4635)
• [core] Add layer block that returns colored wire (by @seldridge in #4623)
• Add UnitTest marker and test discovery utility (by @fabianschuiki in #4642)
• [chiselsim] Add Default (non-Ephemeral) Simulator (by @seldridge in #4665)
• [Chiselsim] Add WithTestingDirectory (by @seldridge in #4669)
• [chiselsim] Rewrite EphemeralSimulator in terms of DefaultSimulator (by @seldridge in #4675)
• [chiselsim] Add, use HasSimulator type class (by @seldridge in #4678)
• [firrtl] Add, use dramaticMessage (by @seldridge in #4684)
• [chiselsim] Add SimulatorAPI, reduce DefaultSimulator to nothing (by @seldridge in #4680)
• [chiselsim] Add ChiselSim APIs (by @seldridge in #4685)
• Add simple API for generating testharnesses inline (by @tmckay-sifive in #4629)
  Add an API to generate testharnesses inline that are emitted as additional public modules in the output.
• Dev/seldridge/switch to chisel settings (by @seldridge in #4708)
• Add RequireProperty and EnsureProperty (by @fabianschuiki in #4681)
• [chiselsim] Add FIRRTL macro control (by @seldridge in #4699)
• [Chiselsim] Replace Chiselspec w/ ChiselSim (by @seldridge in #4706)
• [testing] Add FileCheck API (by @seldridge in #4749)
• Add formal contracts (by @fabianschuiki in #4682)
• [testing] Add HasTestingDirectory subdir factory (by @seldridge in #4774)
• [chiselsim] Allow command line options to be passed to ChiselSim tests (by @seldridge in #4773)
• [scalatest] Add HasCliSimulator (by @seldridge in #4776)
• Change Data._fromUInt to protected (by @jackkoenig in #4782)
  This enables external libraries like FixedPoint to override it. This is not an ideal API, but it works until we have a better way to do this.
• [chiselsim] Add ControlAPI w/ Waveform Enable/Disable Support (by @seldridge in #4779)
• [ChiselSim] Factor reset procedure out of SimulatorAPI and into stimulus (by @seldridge in #4784)
• Add resetType to inline test TestParameters (by @tmckay-sifive in #4789)
  • Add resetType to chisel3.experimental.inlinetest.TestParameters. It will now be easier to properly handle DUTs with uninferred resets.
• [svsim] Add coverage collection to VCS backend (by @seldridge in #4793)
• [svsim][chiselsim] Add plusarg support (by @seldridge in #4796)
• [chiselsim] Add CLI FSDB, VPD support, enable waves (VCD, too) (by @seldridge in #4797)
• [chiselsim] Add waves at time zero to settings (by @seldridge in #4801)
• Provide custom error for Mem masked write wrong data type (by @jackkoenig in #4805)
  The old error was Cannot prove that chisel3.UInt <:< chisel3.Vec[_], the new error is Masked write requires that the data type is a Vec, got chisel3.UInt.
• [chiselsim] HasCliOptions, EmitVcd for ChiselSim (by @seldridge in #4807)
• [chiselsim] Chisel/firtool update type classes (by @seldridge in #4808)
• [svsim] Add Coverage Directory and Name to VCS Backend (by @seldridge in #4812)
• [chiselsim] Add subdirectory to SimulatorAPI fns (by @seldridge in https://github.com/chipsalliance/chisel/pull/...

This release primarily exists to help get users ready for the coming Chisel 7 release--there are several advanced APIs that are now deprecated and will be removed in the Chisel 7.0 release.

API Deprecation

• Add ElaboratedCircuit and deprecate use of internal ir Circuit (backport #4683) (by @chiselbot in #4693)
  Change ChiselCircuitAnnotation and CircuitSerializationAnnotation to no longer be case classes to help with the transition to ElaboratedCircuit.
• Add safer Chisel annotation API, deprecate old ones (backport #4643) (by @chiselbot in #4697)
  Creating annotations in Chisel now requires reporting what InstanceIds are going to be annotated so that Chisel can do some safety checks.
• [testers] Deprecate everything the testers package (backport #4742) (by @chiselbot in #4743)
• Mass deprecations, to be removed in Chisel 7 (backport #4754) (by @chiselbot in #4756)
• Warn on .asUInt|.asSInt(_: Int) (backport #4764) (by @chiselbot in #4766)
  The user probably forgot .W. Apply the same technique as used for .U|.S.

Performance

• Speedup Computation for whether Aggregates containsProbe (backport #4656) (by @chiselbot in #4664)
  Add a private containsProbe var to Aggregate and use it to speed up containsProbe checks.

Fixes

• fix up extra waveform dump behavior in svsim (backport #4592) (by @mergify[bot] in #4600)
• Fixes sendBits()'s handling of signed numbers in svsim (backport #4599) (by @jackkoenig in #4606)
• Deterministic FibonacciLFSR reductions (backport #4688) (by @chiselbot in #4690)
• Escape special characters in Property String literals (backport #4564) (by @mergify[bot] in #4565)
  This technically breaks backwards compatibility for firrtl.ir.StringPropertyLiteral but firrtl.ir is considered an internal API.
• Dev/biancolin/fix module choice under di (backport #4569) (by @mergify[bot] in #4570)
• Support boring on original Module after .toInstance call (backport #4602) (by @mergify[bot] in #4604)

Documentation

• fix typo in SourceInfoTransform.scala (backport #4594) (by @mergify[bot] in #4597)
  Fix typo in scaladoc for sourceInfoTransform macro

Dependency Updates

• Cross-compile the plugin for Scala 2.13.16 (by @jackkoenig in #4692)

Build and Internal Changes

• Update CD permissions for uploading release artifacts (backport #4529) (by @mergify[bot] in #4531)
  Also bump softprops/action-gh-release to v2.1.0.
• [6.x] Enable MiMa for v6.6.0 (by @chiselbot in #4527)

Full Changelog: v6.6.0...v6.7.0

Features

• Implement Lookupable for HasTarget (used by SRAM) (backport #4481) (by @mergify[bot] in #4482)
• Allow BoringUtils to use existing port in a closed module (backport #4484) (by @mergify[bot] in #4486)
  When trying to drill a port, it doesn't matter if the module is closed. We do not need to construct new hardware and can just use the existing port.
• Implement Lookupable for Unit (backport #4497) (by @mergify[bot] in #4498)

API Modification

• Deprecate all Injecting Aspect Code (backport #4415) (by @mergify[bot] in #4416)

API Deprecation

• Deprecate more Aspect parts (backport #4420) (by @mergify[bot] in #4421)

Fixes

• Remove unnecessary overrides of lref and ref in Property (backport #4309) (by @mergify[bot] in #4310)
  This fixes an issue with views of List of Property.
• Improve error messages for empty Mux1H and PriorityMux (backport #4391) (by @mergify[bot] in #4393)
• Handle define on views of Probes (backport #4308) (by @mergify[bot] in #4311)
• Support BoringUtils.bore on OpaqueType wrapping a Property. (backport #4337) (by @mergify[bot] in #4338)
  This ensures boring from an OpaqueType that wraps a Property uses the correct connection operator in the IR.
• Make it legal to extract zero bits from a zero-width UInt (backport #4445) (by @mergify[bot] in #4447)
• Fix Arg.name and earlyLocalName for probes (backport #4359) (by @mergify[bot] in #4360)
• Fix Boring.rwTap on instance ports (backport #4451) (by @mergify[bot] in #4452)
  BoringUtils.rwTap can now works on a port of an instance: Instance[..]
• Fix Select.attachedTo (backport #4458) (by @mergify[bot] in #4461)
• Fix missing string interpolators, add -Xlint:missing-interpolator (backport #4471) (by @mergify[bot] in #4473)
• Add Probes to .toString Data methods (backport #4478) (by @mergify[bot] in #4480)
  Probe chisel types now include the kind of probe and layer in their .toString method

Documentation

• Improve the error message for mismatched types in Mux (backport #4331) (by @mergify[bot] in #4332)

Dependency Updates

• [6.x] Bump to CIRCT 1.62.1 (by @jackkoenig in #4387)
  • [FIRRTL] LowerToHW: guard against folded operations (llvm/circt#7358)
• Add Scala 2.13.15 to compiler plugin cross-build (backport #4410) (by @mergify[bot] in #4413)
  Add support for Scala 2.13.15

Build and Internal Changes

• Add permissions to website deployment job (backport #4285) (by @mergify[bot] in #4290)
• [6.x] Enable MiMa for v6.5.0 (by @chiselbot in #4279)

Full Changelog: v6.5.0...v6.6.0

Features

• Add getClassType API to Definition[T <: Class]. (by @mikeurbach in #3877)
  This allows users to get a ClassType for use in other Property types, which is especially useful when constructing aggregate Property types of a specific Class.
• Add suggestName method to HasTarget (by @debs-sifive in #3881)
  HasTarget trait now also exposes suggestName method of a NamedComponent.
• Print the optional Printable passed to stop ops (by @nandor in #3886)
  The message passed to stop is no longer ignored. The construct was extended to accept Printable.
• Add DeletedPath for targets that no longer exist. (by @mikeurbach in #3937)
  Sometimes a generator wants to emit a Path that targets some Data, but that Data isn't always produced by the generator. The DeletedPath can be used to represent the presence of a Path, but the absence of a Data in this case.
• Make firtool options for elaborateGeneratedModule in workspace parametric (by @rameloni in #3952)
  This adds the support in Chiselsim to configure the workspace with additional args for firtool (#3932). The user can specify how the sv circuit is compiled for simulation (i.e. including debug information -g).
• Add a new BoringUtils.drive API for boring to drive a sink. (by @mikeurbach in #3960)
  This API allows users to bore to a sink they plan to drive, which complements the existing API to bore from a source to read.
• Add requireIsAnnotatable for better errors when annotating literals (by @jackkoenig in #3968)
  This gives much better error messages when accidentally dontTouching a literal
• Add extension points on Data for customizing Connectable behavior. (by @mikeurbach in #3978)
  The user can override these methods to customize how their Data applies waive, squeeze, and exclude in its Connectable.
• Add support for generic intrinsic expressions and statements. (by @dtzSiFive in #3986)
  Intrinsic expressions and statements are now supported, streamlining their use. These should be preferred over intrinsicModule's, which in the future will be deprecated and removed.
• make SerializableModuleGenerator work with D/I (by @sequencer in #4003)
• Add Instanitate.definition to get Definition from cache. (by @sequencer in #4020)
• Add private Module API and internal DataMirror API for moduleIOs. (by @mikeurbach in #4036)
  The DataMirror API allows users who know what they're doing to access a module's ports before it is closed.
• [LTL] Added overloadings for AssertProperty (by @dobios in #4037)
• [Formal] Expose Btor2 target (by @dobios in #4035)
  • [Formal] Allow for Chisel to be compiled to btor2 for Bounded Model Checking using ChiselStage.emitBtor2.
• Add modulePorts and fullModulePorts in DataMirror for Instance (by @debs-sifive in #4076)
  Added modulePorts and fullModulePorts methods in DataMirror that returns all ports on an Instance of a module.
• Add .toRelativeTargetToHierarchy (by @mwachs5 in #4067)
  Add .toRelativeTargetToHierarchy for getting .toRelativeTarget functionality when the root is a Definition or Instance.
• Don't ... top of stack trace if it isn't actually trimmed (by @jackkoenig in #4142)
• [LTL] Add support for new sequence and property ops (by @dobios in #4120)
  • [LTL] Add support for intersect, repeat, gotoRepeat, and nonConsecutiveRepeat ops.
• PeekPokeAPI: include source location on failed expect() calls. (by @kivikakk in #4144)
  SimulationData.expect calls now record source location and report it in the FailedExpectationException on failure.
• Preserve literals across .asUInt (by @jackkoenig in #4148)
  This is mostly useful for initial values for async reset registers and for constructing literal values in testing contexts (e.g. ChiselSim). It also should slightly reduce memory use and .fir size.
• Preserve literal value across .asSInt and .zext (by @jackkoenig in #4151)
• Preserve UInt and SInt literals across .pad (by @jackkoenig in #4156)
• Add support for marking things as readOnly (by @jackkoenig in #4190)
  Users can call .readOnly on any Data to prevent connections to the returned value. Resolves #1267.
• Add ChiselStage.emitCHIRRTLFile (by @jackkoenig in #4232)
  Emits a file without returning the serialized object which is more memory efficient and supports > 2 GiB of serialized FIRRTL text.
• Make requireTypeEquivalent public and add context message (by @mwachs5 in #4243)
  Make Add a contextual message to Data.requireTypeEquivalent and expose a public API in DataMirror.requireTypeEquivalent, to make it easier for user code to have good error messages when requiring type equivalence between two chisel Datas
• Add map method for Valid (by @tymcauley in #4255)
  Users can now apply a function f to the bits field of a Valid instance with the new Valid.map(f) method.
• Add more information when probe types don't match (by @mwachs5 in #4269)
  Add more information to the error message when attempting to probe.define to a mismatched chisel type.

API Modification

• Fix tests to avoid inferred width ports on public modules. (by @dtzSiFive in #3869)
  Main module are "public" (#3813, soon mandatory) which means they cannot have inferred widths or abstract resets. Code relying on old behavior will presently encounter an error in firtool.
• Remove circt.Intrinsic annotation. (by @dtzSiFive in #3945)
  IntrinsicModules (intmodule's in FIRRTL) have replaced this entirely for some time now.
• [svsim] Expose further verilator options for trace file name and simulation speed optimization (by @kammoh in #3985)
• Make AssertPropertyLike.createIntrinsic protected (by @jackkoenig in #4058)
  It should never have been a public API
• checkTypeEquivalence now considers ProbeInfo (by @mwachs5 in #4064)
  Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).
• Make "deprecated public" binding APIs private (by @jackkoenig in #4177)
  These chisel3.internal APIs should never have been public in the first place.
• Fix width of ChiselEnum values in emitted FIRRTL (by @jackkoenig in #4200)
  Fixes #4159.
  Previously, the width reported by Chisel under .getWidth was inconsistent with the width of the emitted FIRRTL for ChiselEnum values cast to UInt.
  Temporarily preserve the old behavior under CLI option --use-legacy-width (formerly known as --use-legacy-shift-right-width). Users are encouraged to build Verilog with and without this option enabled and diff the result to verify that this change in width behavior did not silently affect the correctness of their designs.
• Preserve literals across .asTypeOf (by @jackkoenig in #4168)
  Casting a literal (of any type) to another type with .asTypeOf will result in a literal of the new type. For non-literals, the FIRRTL representation will now be a little bit more efficient.
• Intern Width (by @jackkoenig in #4242)
  • UnknownWidth becomes a case object (Drop () when using it).
  • KnownWidths 0-1024 are interned
• SourceInfo: simplify the common case for makeMessage, print it differently (by @mwachs5 in #4249)
  Add a default to SourceInfo.makeMessage() so that users don't always have to write makeMessage(x => x). Change the toString of SourceLine so that it puts a colon instead of a space between the file name and line number, which makes it possible to click-to-source in editors like VSCode.
• Micro-optimize Direction (by @jackkoenig in #4251)
  • Specified and actual direction information are each now stored as single bytes rather than references.
  • This reduces the memory use of a typical bound UInt from 72 bytes shallow, 128 bytes retained to 64 bytes shallow, 120 bytes retained.
  • The change is mostly source compatible, but ActualDirection.Bidirectional, has changed slightly to memoize its two possibilities (Bidirectional.Default and Bidirectional.Flipped). There are deprecations for the typical APIs

API Deprecation

• IntrinsicModule: deprecate in favor of intrinsic expressions. (by @dtzSiFive in #4060)
  IntrinsicModule has been replaced by Intrinsic and IntrinsicExpr ...

Features

• Don't ... top of stack trace if it isn't actually trimmed (backport #4142) (by @mergify[bot] in #4143)
• PeekPokeAPI: include source location on failed expect() calls. (backport #4144) (by @mergify[bot] in #4149)
  SimulationData.expect calls now record source location and report it in the FailedExpectationException on failure.
• Preserve literals across .asUInt (backport #4148) (by @mergify[bot] in #4150)
  This is mostly useful for initial values for async reset registers and for constructing literal values in testing contexts (e.g. ChiselSim). It also should slightly reduce memory use and .fir size.
• Preserve literal value across .asSInt and .zext (backport #4151) (by @mergify[bot] in #4152)
• Preserve UInt and SInt literals across .pad (backport #4156) (by @mergify[bot] in #4157)
• Add support for marking things as readOnly (backport #4190) (by @mergify[bot] in #4194)
  Users can call .readOnly on any Data to prevent connections to the returned value. Resolves #1267.
• Add ChiselStage.emitCHIRRTLFile (backport #4232) (by @mergify[bot] in #4234)
  Emits a file without returning the serialized object which is more memory efficient and supports > 2 GiB of serialized FIRRTL text.
• Make requireTypeEquivalent public and add context message (backport #4243) (by @mergify[bot] in #4247)
  Make Add a contextual message to Data.requireTypeEquivalent and expose a public API in DataMirror.requireTypeEquivalent, to make it easier for user code to have good error messages when requiring type equivalence between two chisel Datas
• Add map method for Valid (backport #4255) (by @mergify[bot] in #4258)
  Users can now apply a function f to the bits field of a Valid instance with the new Valid.map(f) method.
• Add more information when probe types don't match (backport #4269) (by @mergify[bot] in #4270)
  Add more information to the error message when attempting to probe.define to a mismatched chisel type.

API Deprecation

• Mark return value of .asTypeOf as "deprecated read-only" (backport #4198) (by @mergify[bot] in #4199)
  Previously, .asTypeOf would return a Wire. To get the old behavior, wrap the .asTypeOf call in WireInit(...).
• [LTL] Deprecate disable intrinsic (backport #4237) (by @mergify[bot] in #4239)

Performance

• Share ChildBinding objects between siblings (backport #4238) (by @mergify[bot] in #4241)
  This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
• Move circuitVar from HasId to BaseModule (backport #4253) (by @mergify[bot] in #4263)
  • This removes a 4-byte field (8-bytes with heap > 32 GB) from all Data
• Optimize Record._elements to not duplicate VectorMap if possible (backport #4254) (by @mergify[bot] in #4265)
  This reduces memory use of a typical bundle by 20%.
• Remove autoSeedVar, use Boolean to distinguish suggested or autoSeed (backport #4252) (by @mergify[bot] in #4262)
  • Combined with #4251, reduces the memory use of a typical bound UInt from 64 bytes shallow, 120 bytes retained, to 56 bytes shallow, 112 bytes retained.
• Optimize .readOnly to only create views when necessary (backport #4271) (by @mergify[bot] in #4273)
• Share Node objects between siblings (backport #4259) (by @mergify[bot] in #4272)
  This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
• Specialize Index for literal indices with LitIndex (backport #4268) (by @mergify[bot] in #4274)
  This saves 16-bytes per Vec element.

Fixes

• Suppress exception throwing in Data.toString (backport #4147) (by @mergify[bot] in #4153)
  This makes .toString behavior better outside of Chisel elaboration contexts.
• Error when calling define targeting a child of a probe (backport #4175) (by @mergify[bot] in #4176)
  This is already an error caught in firtool, now Chisel will error earlier.
• Support XMRs to Analog in D/I (backport #4181) (by @mergify[bot] in #4183)
• Distinguish identity views from single-target views (backport #4186) (by @mergify[bot] in #4189)
  Fixes #4185, Fixes #4187
• Initialize scala.util.control.NonFatal in Builder (backport #4195) (by @mergify[bot] in #4197)
• Fix BoringUtils for identity views (backport #4220) (by @mergify[bot] in #4221)
• Name the targets of identity views (backport #4222) (by @mergify[bot] in #4225)
• Make isView safe outside of Builder context (backport #4228) (by @mergify[bot] in #4231)
• Emit FIRRTL bulk connects even for "input" wires (backport #4219) (by @mergify[bot] in #4235)
• Use :<>= in VecInit methods instead of := or <> (backport #4248) (by @mergify[bot] in #4250)
  Previously, VecInit would try to "intelligently" select := or <> depending on if the type is bidirectional. :<>= has the desirable behavior here for both passive and bidirectional types. It also has the advantage over <> of handling internal wires.
• Fix .toString for dynamic indexing (backport #4260) (by @mergify[bot] in #4267)

Documentation

• Add a test for issue 4159 (backport #4161) (by @mergify[bot] in #4166)
• Add more exhaustive tests for .asTypeOf (backport #4160) (by @mergify[bot] in #4169)
• Fix import path in docstring (backport #4256) (by @mergify[bot] in #4257)

Build and Internal Changes

• [6.x] Enable MiMa for v6.4.0 (by @chiselbot in #4127)

Full Changelog: v6.4.0...v6.5.0

Features

• Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in #3213)
• Allow DataView of Reset <=> [UInt<1>, AsyncReset] (backport #3181) (by @mergify[bot] in #3258)
• Fix color emission to check for interactive terminal (backport #3334) (by @mergify[bot] in #3335)
  • Chisel will now detect when it should print warnings, errors, and deprecations in color.
    • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
    • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
• Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #3228) (by @mergify[bot] in #3361)
  This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
• SRAM API: Add a parameter to initialize the memory (backport #3364) (by @mergify[bot] in #3379)
  SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
• Support literals and DontCare in DataView targets (backport #3389) (by @mergify[bot] in #3390)
• SRAM API: Add multiple-clocked port API (backport #3383) (by @mergify[bot] in #3404)
  Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
• Add Instance.suggestName (backport #2886) (by @mergify[bot] in #3723)
  Adds suggestName API for hierarchy instances.
• Implement typeName API for stable Module names (backport #3130) (by @mergify[bot] in #4145)
  This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues

API Deprecation

• Deprecate calling .viewAs on non-hardware (backport #3395) (by @mergify[bot] in #3399)
  Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.

Backend Code Generation

• Don't emit nodes when calling .asBool on a Bool (backport #3637) (by @mergify[bot] in #3638)
  This results in a slight improvement to emitted FIRRTL quality

Performance

• Optimize BitPat equals, overlap, and cover (backport #3285) (by @mergify[bot] in #3287)
• Convert Vec dynamic index with a literal to static index (backport #3314) (by @mergify[bot] in #3318)
• Fix issue where reify would do the same lookup twice (backport #3392) (by @mergify[bot] in #3396)

Fixes

• Fix Instantiate for Product parameters (backport #3210) (by @mergify[bot] in #3217)
• Don't emit implicit clock warnings for SyncReadMem.readWrite when explicit clocks are used (backport #3313) (by @mergify[bot] in #3315)
• Report Builder errors even when exception is thrown (backport #3341) (by @mergify[bot] in #3342)
  Chisel will to report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
• Add messages to require statements in Math (backport #3385) (by @mergify[bot] in #3387)
  • log2 functions
    • unsignedBitLength
• Sanitize Record._elements (backport #3419) (by @mergify[bot] in #3426)
  Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
• Fix DataMirror.internal.chiselTypeClone to preserve Scala type (backport #3553) (by @mergify[bot] in #3554)
• Fix Decodetable (backport #3563) (by @mergify[bot] in #3579)
• Add type ascription to implicits from instantiable (backport #3615) (by @mergify[bot] in #3617)
  This fixes Scala compiler warnings in Scala 2.13.12 requiring type ascriptions on public implicit definitions.
• Support === on empty Aggregates (backport #3747) (by @mergify[bot] in #3749)
• Fix Reg() to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in #3778)
  • Clocks are now properly supported by DataView (including FlatIO)
  • Users will also received better error messages when providing invalid clocks to Reg()
• Report source locator in when scoping error messages (backport #3804) (by @mergify[bot] in #3806)
• Fix === for abstract Reset types (backport #3979) (by @mergify[bot] in #3980)
  Previously, the function would infinitely recurse resulting in a stack overflow.
• Fix widths for literal values in Bundle literals (backport #4082) (by @mergify[bot] in #4090)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.

Documentation

• [fix] typo fix: chosen port of arbiter is not onehot but UInt (backport #3235) (by @mergify[bot] in #3260)
  Just a oneline fix to the comment of Arbiter chosen port
• Changed Array to Seq in MuxLookup explantation (backport #3547) (by @mergify[bot] in #3549)
• Update CONTRIBUTING.md (backport #3785) (by @mergify[bot] in #3786)
  Update CONTRIBUTING instructions to clarify backport process and branch to target.
• [website] Update chisel-template repo link to chipsalliance (backport #3871) (by @mergify[bot] in #3894)
• Rename Scala CLI template to example (backport #3917) (by @mergify[bot] in #3918)
  Existing links to https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
• Add a test for issue 4159 (backport #4161) (by @mergify[bot] in #4164)

Dependency Updates

• Add Scala 2.13.11 and 2.12.18 to plugin cross versions (backport #3327) (by @mergify[bot] in #3329)
• Add support for Scala 2.13.12 to the compiler plugin (backport #3527) (by @mergify[bot] in #3529)
• Add Scala 2.13.13 to cross-build (backport #3851) (by @mergify[bot] in #3862)
• Add Scala 2.13.14 to cross-build (backport #4044) (by @mergify[bot] in #4045)

Build and Internal Changes

• Read previousVersions for bincompat checking from a file (backport #3202) (by @mergify[bot] in #3207)
• Add workflow to automatically update binary compatibility checks (backport #3242) (by @mergify[bot] in #3249)
• Add new workflow to fixup backports for release notes (backport #3252) (by @mergify[bot] in #3253)
  Improve backport automation so that release notes generation from backport PRs works properly.
• SemanticDB requires private fields of case class to use "val" (backport #3270) (by @mergify[bot] in #3271)
• Fix BuildInfo in 3.6.x (by @sequencer in #3371)
• Update Scala CLI Template (backport #3757) (by @mergify[bot] in #3758)
  • Use "dep" instead of deprecated "lib"
  • Move ChiselStage import above import chisel3._
    • This makes users less likely to run into issues adding import chisel3.util._
  • Bump versions in Github workflows
• Enhance release notes automation (backport #3751) (by @mergify[bot] in #3776)
  • Bump mikepenz/release-changelog-builder-action to v4.1.1
  • It now tabs every line included in the Release Notes section of the PR template
• [ci] Stop copying body over to backports in backport-fixup (backport #4005) (by @mergify[bot] in #4048)
• [3.6.x] Modernize Release Flow (by @jackkoenig in https://g...

Features

• [LTL] Added overloadings for AssertProperty (backport #4037) (by @mergify[bot] in #4041)
• Add modulePorts and fullModulePorts in DataMirror for Instance (backport #4076) (by @mergify[bot] in #4077)
  Added modulePorts and fullModulePorts methods in DataMirror that returns all ports on an Instance of a module.

API Modification

• checkTypeEquivalence now considers ProbeInfo (backport #4064) (by @mergify[bot] in #4112)
  Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).

API Deprecation

• Deprecate AssertPropertyLike.createIntrinsic (by @jackkoenig in #4059)
  It should never have been a public API.
• Make it a warning to have too-wide literal values in Bundle Literals (backport #4093) (by @mergify[bot] in #4095)

Fixes

• Fix Nested Instantiate (backport #4018) (by @mergify[bot] in #4027)
  Fix Nested Instantiate
• Fix Typo in ExtractFromVecSizeZero warning message (backport #4029) (by @mergify[bot] in #4031)
• Add support for Vec literals of empty Vecs (backport #4070) (by @mergify[bot] in #4073)
• Fix literal handling for views of empty Aggregates (backport #4071) (by @mergify[bot] in #4075)
  Previously, a view of an empty aggregate would incorrectly always have a litValue of 0.
• Materialize wires for .ref of Aggregate views (backport #4080) (by @mergify[bot] in #4086)
  Fix muxing and probing of views of Aggregates
• [SVSim] Fixed non-firing AssertProperty in SVSim (backport #4087) (by @mergify[bot] in #4089)
  • [SVSim] Fixed AssertProperty failing to fire in verilator simulation.
• Fix widths for literal values in Bundle literals (backport #4082) (by @mergify[bot] in #4092)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
• BoringUtils: Fix tapAndRead to return same type even when not boring. (backport #4084) (by @mergify[bot] in #4094)
  Always return fully aligned result from tapAndRead, even if no boring performed.
• Don't warn when 0.U used as value for 0-bit BundleLit field (backport #4097) (by @mergify[bot] in #4098)
• Fix boring tap of non-passive source from parent. (backport #4083) (by @mergify[bot] in #4096)
  Fix tapping mix-alignment signal from parent.
• Fix 0 width signals chiselsim (backport #4100) (by @mergify[bot] in #4104)
  Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.
• Support views of ports in ChiselSim (backport #4107) (by @mergify[bot] in #4110)
  Also fix reifySingleData to return the Data itself if it is not a view.
• FixedIO__Modules with various kinds of probe ports (backport #4105) (by @mergify[bot] in #4111)
  Fix for #4102. Now supported are FlatIO (and therefore FixedIO___Module) of:
  • Probe(Element)
  • Probe(Aggregate)
  • Aggregate(Probes)
  • Aggregates containing any of the above
• Fix svsim with gcc14 (backport #4121) (by @mergify[bot] in #4123)

Dependency Updates

• Add Scala 2.13.14 to cross-build (backport #4044) (by @mergify[bot] in #4047)

Build and Internal Changes

• [6.x] Enable MiMa for v6.3.0 (by @chiselbot in #4017)
• [ci] Stop copying body over to backports in backport-fixup (backport #4005) (by @mergify[bot] in #4043)
• add test for FlatIO port ordering (backport #4113) (by @mergify[bot] in #4115)
  Added a unit test for FlatIO Ordering being maintained
• Bump versions of Github actions to versions using Node 20 (backport #4116) (by @mergify[bot] in #4118)
• Add and use Mill wrapper script (backport #4119) (by @mergify[bot] in #4125)

Full Changelog: v6.3.0...v6.4.0

Fixes

• Fix Nested Instantiate (backport #4018) (by @mergify[bot] in #4026)
  Fix Nested Instantiate
• Add support for Vec literals of empty Vecs (backport #4070) (by @mergify[bot] in #4072)
• Fix literal handling for views of empty Aggregates (backport #4071) (by @mergify[bot] in #4074)
  Previously, a view of an empty aggregate would incorrectly always have a litValue of 0.
• [SVSim] Fixed non-firing AssertProperty in SVSim (backport #4087) (by @mergify[bot] in #4088)
  • [SVSim] Fixed AssertProperty failing to fire in verilator simulation.
• Materialize wires for .ref of Aggregate views (backport #4080) (by @mergify[bot] in #4085)
  Fix muxing and probing of views of Aggregates
• Fix widths for literal values in Bundle literals (backport #4082) (by @mergify[bot] in #4091)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
• Fix 0 width signals chiselsim (backport #4100) (by @mergify[bot] in #4103)
  Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.
• Fix svsim with gcc14 (backport #4121) (by @mergify[bot] in #4122)

Dependency Updates

• Add Scala 2.13.14 to cross-build (backport #4044) (by @mergify[bot] in #4046)
• Add 2.12.19 to cross-build (by @jackkoenig in #4050)

Build and Internal Changes

• [5.x] Enable MiMa for v5.2.0 (by @chiselbot in #4016)
• [ci] Stop copying body over to backports in backport-fixup (backport #4005) (by @mergify[bot] in #4042)
• add test for FlatIO port ordering (backport #4113) (by @mergify[bot] in #4114)
  Added a unit test for FlatIO Ordering being maintained
• Bump versions of Github actions to versions using Node 20 (backport #4116) (by @mergify[bot] in #4117)
• Add and use Mill wrapper script (backport #4119) (by @mergify[bot] in #4124)

Full Changelog: v5.2.0...v5.3.0