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SCCL is an open-source tool that translates synthesizable SystemC to SystemVerilog RTL. This project started out as front-end for parsing and analyzing SystemC models, and it has evolved into a translator with the addition of a HDL synthesis plugin.
It is possible to build the documentation by specifying the -DBUILD_DOC=ON flag. This will provide the following targets
doxygen: Builds Doxygen documentation.
sphinx : Builds Sphinx documentation.
Tests
To enable compilation of tests, run cmake with the -DENABLE_TESTS=on flag and also the -DSYSTEMC_DIR=<path> flag to pass the location for SystemC. Without specifying the SYSTEMC_DIR path, it will not be possible to run the unit tests.
For information about running verilog conversion tests, see this file.
ASIC flow
We have successfully been able to use the open-source ASIC flow in siliconcompiler to generate the chip for ZFP's encoder. The input to siliconcompiler is the RTL generated by SCCL. Below is what we got.
Issues
If you encounter problems, please create issues with a minimally working example that illustrates the issue.
Development Docker image
We build all the dependencies necessary for SCCL in a Docker image that you may use. Follow these Docker SCCL instructions to use the Docker image for building SCCL, and running benchmarks.
Project Ideas
If you're interested in contributing to SCCL, then we keep a list of interesting projects that one could approach. Please consult projects.
Publications
Zhuanhao Wu, Maya Gokhale, Scott Lloyd and Hiren Patel, SCCL: An open-source SystemC to RTL translator, 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Marina Del Rey, CA, USA, 2023, pp. 23-33, doi: 10.1109/FCCM57271.2023.00012.