Fix some typos (yeild_op, yeild_info, etc.) (#61833)

co63oc · web-flow · commit b8be0c7be0b8 · 2024-02-21T14:36:11.000+08:00
* Fix

* Fix
diff --git a/paddle/cinn/hlir/dialect/operator/transforms/lower_cinn_fusion_op_pass.cc b/paddle/cinn/hlir/dialect/operator/transforms/lower_cinn_fusion_op_pass.cc
@@ -88,7 +88,7 @@ bool EraseOneExpand(
   return false;
 }
 
-void EraseUneccessaryExpandsInBlock(
+void EraseUnnecessaryExpandsInBlock(
     pir::Block* block,
     pir::PatternRewriter& rewriter,  // NOLINT
     const ShapeOrDataDimExprs4ValueT& ShapeOrDataDimExprs4Value) {
@@ -393,7 +393,7 @@ pir::Operation* CreateConditionBlock(
 }
 
 std::unordered_map<GroupPtr, std::unordered_map<std::string, pir::Attribute>>
-ComplieGroupAsOpAttribute(
+CompileGroupAsOpAttribute(
     const std::shared_ptr<cinn::hlir::framework::PirCompiler>& pir_compiler,
     const std::vector<GroupPtr>& group_list) {
   auto fn_ptr_res = pir_compiler->BuildCUDAJITInfo(group_list);
@@ -438,7 +438,7 @@ void SimplyConditionBlock(
         [&group](pir::Value value) -> const symbol::ShapeOrDataDimExprs& {
       return group->GetShapeOrDataExprs(value);
     };
-    EraseUneccessaryExpandsInBlock(block, rewriter, GetShapeOrDataForValue);
+    EraseUnnecessaryExpandsInBlock(block, rewriter, GetShapeOrDataForValue);
   });
   ForEachMutBlockGroup([&](auto* block, const auto& group) {
     ReplaceExpandWithBroadcast(rewriter.ir_context(), block, group);
@@ -456,17 +456,17 @@ void CompileGroupToJitKernelOp(
   for (const auto& [_, group] : *group_map) {
     group_list.push_back(group);
   }
-  auto op_attr_map = ComplieGroupAsOpAttribute(pir_compiler, group_list);
+  auto op_attr_map = CompileGroupAsOpAttribute(pir_compiler, group_list);
   VLOG(4) << "The size of group_map is : " << group_map->size();
   for (auto& [block, group] : *group_map) {
     std::vector<pir::Type> output_types;
     const auto& group_output_values = group->output_values;
     for (size_t i = 0; i < group_output_values.size(); ++i) {
       output_types.push_back(group_output_values[i].type());
     }
-    auto& yeild_op = block->back();
-    CHECK(yeild_op.isa<pir::YieldOp>()) << "Last op of block should be yield";
-    rewriter.set_insertion_point(&yeild_op);
+    auto& yield_op = block->back();
+    CHECK(yield_op.isa<pir::YieldOp>()) << "Last op of block should be yield";
+    rewriter.set_insertion_point(&yield_op);
     auto jit_kernel_op = rewriter.Build<cinn::dialect::JitKernelOp>(
         group_inputs, op_attr_map.at(group), output_types);
     CHECK(jit_kernel_op.num_results() == group_output_values.size());
@@ -490,7 +490,7 @@ void CompileGroupToJitKernelOp(
   }
 }
 
-pir::Operation* ComplieBroadcastTreeToConditionBlock(
+pir::Operation* CompileBroadcastTreeToConditionBlock(
     const cinn::common::BroadcastTree& broadcast_tree,
     const GroupPtr& group,
     pir::ShapeConstraintIRAnalysis& shape_analysis,  // NOLINT
@@ -518,9 +518,9 @@ pir::Operation* ComplieBroadcastTreeToConditionBlock(
   SimplyConditionBlock(rewriter, &group_map);
   VLOG(6) << "After simply condition block: " << *program;
 
-  // 3. complie condition block to jit_kernel_op
+  // 3. compile condition block to jit_kernel_op
   CompileGroupToJitKernelOp(group_inputs, pir_compiler, rewriter, &group_map);
-  VLOG(6) << "complie condition block to jit_kernel_op: " << *program;
+  VLOG(6) << "compile condition block to jit_kernel_op: " << *program;
 
   return cond_op;
 }
@@ -571,7 +571,7 @@ pir::Operation* ProcessDyShapeGroup(
     for (size_t i = 0; i < group_output_values.size(); ++i) {
       output_types.push_back(group_output_values[i].type());
     }
-    return ComplieBroadcastTreeToConditionBlock(broadcast_tree,
+    return CompileBroadcastTreeToConditionBlock(broadcast_tree,
                                                 group,
                                                 shape_analysis,
                                                 pir_compiler,
@@ -580,8 +580,8 @@ pir::Operation* ProcessDyShapeGroup(
                                                 output_types,
                                                 rewriter);
   } else {  // no condition block
-    // complie group to jit_kernel_op
-    auto op_attr_map = ComplieGroupAsOpAttribute(pir_compiler, {group});
+    // compile group to jit_kernel_op
+    auto op_attr_map = CompileGroupAsOpAttribute(pir_compiler, {group});
     std::vector<pir::Type> output_types;
     const auto& group_output_values = group->output_values;
     for (size_t i = 0; i < group_output_values.size(); ++i) {
@@ -628,7 +628,7 @@ class FusionOpPattern : public pir::OpRewritePattern<cinn::dialect::FusionOp> {
                        pir::PatternRewriter& rewriter) const override {
     ::pir::IrContext* ctx = ::pir::IrContext::Instance();
     auto target = cinn::common::DefaultNVGPUTarget();
-    // TODO(Aurelius84): Remove scope after cleaning PirCompiler usless Build
+    // TODO(Aurelius84): Remove scope after cleaning PirCompiler useless Build
     // Interface
     auto scope = std::make_shared<cinn::hlir::framework::Scope>();
     auto* program = fusion_op->GetParentProgram();
@@ -648,14 +648,14 @@ class FusionOpPattern : public pir::OpRewritePattern<cinn::dialect::FusionOp> {
     }
 
     // TODO(zhangyuqin1998): Replace pir::Group with a new structure
-    pir::Operation* complied_op =
+    pir::Operation* compiled_op =
         ProcessGroup(group, shape_analysis, ir_compiler, rewriter);
 
     for (size_t i = 0; i < fusion_op.num_results(); ++i) {
-      rewriter.ReplaceAllUsesWith(fusion_op.result(i), complied_op->result(i));
+      rewriter.ReplaceAllUsesWith(fusion_op.result(i), compiled_op->result(i));
       if (shape_analysis.HasShapeOrDataForValue(fusion_op.result(i))) {
         shape_analysis.SetShapeOrDataForValue(
-            complied_op->result(i),
+            compiled_op->result(i),
             shape_analysis.GetShapeOrDataForValue(fusion_op.result(i)));
       } else {
         LOG(WARNING) << "No shape_data for "
@@ -675,8 +675,8 @@ class FusionOpPattern : public pir::OpRewritePattern<cinn::dialect::FusionOp> {
       const std::shared_ptr<cinn::hlir::framework::PirCompiler>& pir_compiler,
       pir::PatternRewriter& rewriter) const {  // NOLINT
     auto group_inputs = GetBlockOutsideInput(group->ops);
-    // complie group to jit_kernel_op
-    auto op_attr_map = ComplieGroupAsOpAttribute(pir_compiler, {group});
+    // compile group to jit_kernel_op
+    auto op_attr_map = CompileGroupAsOpAttribute(pir_compiler, {group});
     std::vector<pir::Type> output_types;
     const auto& group_output_values = group->output_values;
     for (size_t i = 0; i < group_output_values.size(); ++i) {
diff --git a/paddle/fluid/ir_adaptor/translator/program_translator.cc b/paddle/fluid/ir_adaptor/translator/program_translator.cc
@@ -404,7 +404,7 @@ void ProgramTranslator::TranslateIfOperation(
                    true_block_context,
                    &true_region.front());
 
-    // insert tuple_push op to true block before yeild op
+    // insert tuple_push op to true block before yield op
     if (!for_bwd && push_pop_var_names_[op].size() != 0) {
       std::vector<pir::Value> local_values;
       local_values.push_back(cond_to_stack_value_[op][0]);
@@ -421,30 +421,30 @@ void ProgramTranslator::TranslateIfOperation(
       true_region.front().push_back(tuple_push_op);
     }
 
-    // insert yeild op to true block
-    auto yeild_info = ctx_->GetRegisteredOpInfo(pir::YieldOp::name());
-    std::vector<pir::Value> true_yeild_inputs;
+    // insert yield op to true block
+    auto yield_info = ctx_->GetRegisteredOpInfo(pir::YieldOp::name());
+    std::vector<pir::Value> true_yield_inputs;
     for (auto& out_name : cond_op_outputs) {
       if (for_bwd && out_name.find("@RENAME@block") != std::string::npos) {
         out_name = out_name.substr(0, out_name.find("@RENAME@block"));
       }
-      true_yeild_inputs.push_back(true_block_context->at(out_name).value);
+      true_yield_inputs.push_back(true_block_context->at(out_name).value);
     }
     true_region.front().push_back(
-        pir::Operation::Create(true_yeild_inputs, {}, {}, yeild_info));
+        pir::Operation::Create(true_yield_inputs, {}, {}, yield_info));
 
     // NOTE(zhangbo): The if_op of PIR requires that both true and false
     // branches must exist, and the number of outputs and dtypes must be
     // consistent. Only inconsistent shape is allowed. To be compatible with the
     // old IR design, only true branches are allowed. The false branch may
-    // require yeild some fake variables.
+    // require yield some fake variables.
     pir::Region& false_region = if_op->region(1);
     if (false_region.empty()) false_region.emplace_back();
     auto* false_block_context = translation_ctx->CreateInnerContext();
-    std::vector<pir::Value> false_yeild_inputs;
+    std::vector<pir::Value> false_yield_inputs;
     for (size_t id = 0; id < cond_op_outputs.size(); id++) {
       if (false_block_context->count(cond_op_outputs[id]) == 0) {
-        auto true_type = true_yeild_inputs[id].type();
+        auto true_type = true_yield_inputs[id].type();
         pir::Operation* init_op =
             InsertInitOpOrCreateArrayToBlock(&false_region.front(), true_type);
         PADDLE_ENFORCE_NOT_NULL(
@@ -455,11 +455,11 @@ void ProgramTranslator::TranslateIfOperation(
         false_block_context->PushValue(
             cond_op_outputs[id], VariableDefiningInfo(init_op->result(0)));
       }
-      false_yeild_inputs.push_back(
+      false_yield_inputs.push_back(
           false_block_context->at(cond_op_outputs[id]).value);
     }
     false_region.front().push_back(
-        pir::Operation::Create(false_yeild_inputs, {}, {}, yeild_info));
+        pir::Operation::Create(false_yield_inputs, {}, {}, yield_info));
   }
   VLOG(4) << "[general op][conditional_block] IfOp true block translate end.";
 
@@ -512,13 +512,13 @@ void ProgramTranslator::TranslateWhileOperation(
   TranslateBlock(
       sub_block, 0, sub_block.OpSize(), body_block_context, body_block);
 
-  auto yeild_info = ctx_->GetRegisteredOpInfo(pir::YieldOp::name());
-  std::vector<pir::Value> yeild_inputs{body_block_context->at(cond_var).value};
+  auto yield_info = ctx_->GetRegisteredOpInfo(pir::YieldOp::name());
+  std::vector<pir::Value> yield_inputs{body_block_context->at(cond_var).value};
   for (auto& loop_var : loop_vars) {
-    yeild_inputs.push_back(body_block_context->at(loop_var).value);
+    yield_inputs.push_back(body_block_context->at(loop_var).value);
   }
   body_block->push_back(
-      pir::Operation::Create(yeild_inputs, {}, {}, yeild_info));
+      pir::Operation::Create(yield_inputs, {}, {}, yield_info));
   for (size_t idx = 0; idx < loop_vars.size(); ++idx) {
     translation_ctx->PushValue(loop_vars[idx], while_op->result(idx));
   }
