Fix (#65862)

co63oc · web-flow · commit 6a23ce9e0092 · 2024-07-10T09:39:03.000+08:00
diff --git a/paddle/fluid/imperative/all_reduce.cc b/paddle/fluid/imperative/all_reduce.cc
@@ -59,7 +59,7 @@ static void AllReduce(const phi::DenseTensor &src,
                       const platform::NCCLComm *comm) {
   const auto &place = src.place();
   PADDLE_ENFORCE_EQ(
-      platform::is_gpu_place(place),
+      phi::is_gpu_place(place),
       true,
       platform::errors::Unimplemented(
           "Imperative mode does not support multi-CPU training yet."));
@@ -88,7 +88,7 @@ static void AllReduce(const phi::SelectedRows &src,
   const auto &src_tensor = src.value();
   const auto &place = src_tensor.place();
   PADDLE_ENFORCE_EQ(
-      platform::is_gpu_place(place),
+      phi::is_gpu_place(place),
       true,
       platform::errors::Unimplemented(
           "Imperative mode does not support multi-CPU training yet."));
diff --git a/paddle/fluid/imperative/amp_auto_cast.cc b/paddle/fluid/imperative/amp_auto_cast.cc
@@ -48,12 +48,12 @@ OpSupportedInfos(const std::string& place,
                  [](unsigned char c) { return std::toupper(c); });
   using fn_type = std::add_pointer<bool(const platform::Place&)>::type;
   std::unordered_map<std::string, fn_type> is_target_place{
-      {"GPU", &platform::is_gpu_place},
-      {"CPU", &platform::is_cpu_place},
-      {"XPU", &platform::is_xpu_place},
-      {"CUSTOM_DEVICE", &platform::is_custom_place},
+      {"GPU", &phi::is_gpu_place},
+      {"CPU", &phi::is_cpu_place},
+      {"XPU", &phi::is_xpu_place},
+      {"CUSTOM_DEVICE", &phi::is_custom_place},
 #ifdef PADDLE_WITH_CUSTOM_DEVICE
-      {query_place, &platform::is_custom_place},
+      {query_place, &phi::is_custom_place},
 #endif
   };
   PADDLE_ENFORCE_NE(is_target_place.count(query_place),
@@ -274,10 +274,8 @@ template <typename VarType>
 inline bool NeedCast(const std::shared_ptr<VarType>& var) {
   auto place = GetPlace(var);
   auto data_type = GetDataType<VarType>(var);
-  if (paddle::platform::is_gpu_place(place) ||
-      paddle::platform::is_cuda_pinned_place(place) ||
-      paddle::platform::is_xpu_place(place) ||
-      paddle::platform::is_custom_place(place)) {
+  if (phi::is_gpu_place(place) || phi::is_cuda_pinned_place(place) ||
+      phi::is_xpu_place(place) || phi::is_custom_place(place)) {
     // CudaPinnedPlace is added for varbase created by dataloader
     if (data_type == paddle::framework::proto::VarType::FP32 ||
         data_type == paddle::framework::proto::VarType::FP16 ||
diff --git a/paddle/fluid/imperative/amp_utils.h b/paddle/fluid/imperative/amp_utils.h
@@ -107,10 +107,9 @@ static inline phi::DataType GetDtypeWithPlace(
       //       dist-tensor in the no-calculation rank should have the right
       //       place.
       is_right_place =
-          (tensor.is_dist_tensor() || paddle::platform::is_gpu_place(place) ||
-           paddle::platform::is_cuda_pinned_place(place) ||
-           paddle::platform::is_xpu_place(place) ||
-           paddle::platform::is_custom_place(place));
+          (tensor.is_dist_tensor() || phi::is_gpu_place(place) ||
+           phi::is_cuda_pinned_place(place) || phi::is_xpu_place(place) ||
+           phi::is_custom_place(place));
       if (is_right_place) {
         break;
       }
@@ -196,11 +195,9 @@ static inline bool NeedCast(const paddle::Tensor& tensor,
   auto data_type = tensor.dtype();
   // Except CPU judgment, other conditions should be consistent with
   // amp_utils.h's judgment
-  if (paddle::platform::is_gpu_place(place) ||
-      paddle::platform::is_cuda_pinned_place(place) ||
-      paddle::platform::is_xpu_place(place) ||
-      paddle::platform::is_custom_place(place) ||
-      paddle::platform::is_cpu_place(place)) {
+  if (phi::is_gpu_place(place) || phi::is_cuda_pinned_place(place) ||
+      phi::is_xpu_place(place) || phi::is_custom_place(place) ||
+      phi::is_cpu_place(place)) {
     // CudaPinnedPlace is added for varbase created by dataloader
     // Cpu place is for different place tensor, when input1 is cpu and input2
     // is gpu
diff --git a/paddle/fluid/imperative/bkcl_context.cc b/paddle/fluid/imperative/bkcl_context.cc
@@ -39,7 +39,7 @@ static void AllReduce(const phi::DenseTensor &src,
                       const platform::BKCLComm *comm) {
   const auto &place = src.place();
   PADDLE_ENFORCE_EQ(
-      platform::is_xpu_place(place),
+      phi::is_xpu_place(place),
       true,
       platform::errors::Unimplemented(
           "Dynamic graph mode does not support multi-CPU training yet."));
@@ -150,7 +150,7 @@ void BKCLParallelContext::AllReduceByStream(const framework::Variable &src,
                                             int ring_id,
                                             bool use_calc_stream) {
   PADDLE_ENFORCE_EQ(
-      platform::is_xpu_place(place_),
+      phi::is_xpu_place(place_),
       true,
       platform::errors::Unimplemented(
           "Dynamic graph mode does not support multi-CPU training yet."));
diff --git a/paddle/fluid/imperative/gradient_accumulator.cc b/paddle/fluid/imperative/gradient_accumulator.cc
@@ -207,7 +207,7 @@ void TensorAdd(const VarType& src, VarType* dst) {
     return;                                                                    \
   }
 
-  if (platform::is_gpu_place(place)) {
+  if (phi::is_gpu_place(place)) {
 #if defined(PADDLE_WITH_CUDA) || defined(PADDLE_WITH_HIP)
     PADDLE_TENSOR_ADD(float, phi::GPUContext);
     PADDLE_TENSOR_ADD(double, phi::GPUContext);
@@ -227,7 +227,7 @@ void TensorAdd(const VarType& src, VarType* dst) {
   out.device(p) = out + in;                                \
   return;
 
-  if (platform::is_cpu_place(place)) {
+  if (phi::is_cpu_place(place)) {
     PADDLE_TENSOR_ADD(float, phi::CPUContext);
     PADDLE_TENSOR_ADD(double, phi::CPUContext);
     PADDLE_TENSOR_ADD(platform::complex<float>, phi::CPUContext);
@@ -256,7 +256,7 @@ void TensorAdd(const VarType& src, VarType* dst) {
     return;                                                      \
   }
 
-  if (platform::is_custom_place(place)) {
+  if (phi::is_custom_place(place)) {
 #if defined(PADDLE_WITH_CUSTOM_DEVICE)
     PADDLE_TENSOR_ADD_CUSTOM(float);
     PADDLE_TENSOR_ADD_CUSTOM(double);
@@ -266,7 +266,7 @@ void TensorAdd(const VarType& src, VarType* dst) {
   }
 
 #ifdef PADDLE_WITH_XPU
-  if (platform::is_xpu_place(place)) {
+  if (phi::is_xpu_place(place)) {
     if (data_type == framework::DataTypeTrait<float>::DataType()) {
       XPUTensorAddFunctor<float>(place, src_tensor, dst_tensor);
     } else if (data_type ==
@@ -326,7 +326,7 @@ void SelectedRowsAddToTensor(const VarType& src, VarType* dst) {
   }
 
 #if defined(PADDLE_WITH_CUDA) || defined(PADDLE_WITH_HIP)
-  if (paddle::platform::is_gpu_place(place)) {
+  if (phi::is_gpu_place(place)) {
     PADDLE_SELECTED_ROWS_ADD_TO_TENSOR(phi::GPUContext, float);
     PADDLE_SELECTED_ROWS_ADD_TO_TENSOR(phi::GPUContext, double);
   } else {
@@ -381,7 +381,7 @@ void SelectedRowsAddTensor(const VarType& src_selected_rows_var,
   }
 
 #if defined(PADDLE_WITH_CUDA) || defined(PADDLE_WITH_HIP)
-  if (platform::is_gpu_place(place)) {
+  if (phi::is_gpu_place(place)) {
     PADDLE_SELECTED_ROWS_ADD_TENSOR(phi::GPUContext, float);
     PADDLE_SELECTED_ROWS_ADD_TENSOR(phi::GPUContext, double);
   } else {
@@ -447,13 +447,13 @@ std::shared_ptr<ReturnVarType> SelectedRowsMerge(const VarType& src1,
   }
 
 #if defined(PADDLE_WITH_CUDA) || defined(PADDLE_WITH_HIP)
-  if (paddle::platform::is_gpu_place(place)) {
+  if (phi::is_gpu_place(place)) {
     PADDLE_SELECTED_ROWS_ADD(phi::GPUContext, float);
     PADDLE_SELECTED_ROWS_ADD(phi::GPUContext, double);
   } else {
 #endif
 #if defined(PADDLE_WITH_XPU)
-    if (paddle::platform::is_xpu_place(place)) {
+    if (phi::is_xpu_place(place)) {
       PADDLE_SELECTED_ROWS_ADD(phi::XPUContext, float);
     } else {
 #endif
@@ -733,7 +733,7 @@ void SortedGradientAccumulator::SumGrad(std::shared_ptr<VariableWrapper> var,
       }
 
 #if defined(PADDLE_WITH_CUDA) || defined(PADDLE_WITH_HIP)
-      if (paddle::platform::is_gpu_place(place)) {  // NOLINT
+      if (phi::is_gpu_place(place)) {  // NOLINT
         // sum selected rows firstly
         for (auto& var_info : tmp_grad_vars_) {
           if (!var_info.var->Var().IsType<phi::SelectedRows>()) {
diff --git a/paddle/fluid/imperative/nccl_context.cc b/paddle/fluid/imperative/nccl_context.cc
@@ -131,7 +131,7 @@ void NCCLParallelContext::AllReduceByStream(const framework::Variable &src,
                                             int ring_id,
                                             bool use_calc_stream) {
   PADDLE_ENFORCE_EQ(
-      platform::is_gpu_place(place_),
+      phi::is_gpu_place(place_),
       true,
       platform::errors::Unimplemented(
           "Dynamic graph mode does not support multi-CPU training yet."));
diff --git a/paddle/fluid/imperative/prepared_operator.cc b/paddle/fluid/imperative/prepared_operator.cc
@@ -376,7 +376,7 @@ PreparedOp PrepareImpl(
   auto kernel_iter = kernels.find(fluid_kernel_type);
 
 #if defined(PADDLE_WITH_XPU) && !defined(PADDLE_WITH_XPU_KP)
-  if (paddle::platform::is_xpu_place(fluid_kernel_type.place_) &&
+  if (phi::is_xpu_place(fluid_kernel_type.place_) &&
       (kernel_iter == kernels.end() || is_xpu_unsupport)) {
     VLOG(3) << "fluid missing XPU kernel: " << op.Type()
             << ", expected_kernel_key:" << fluid_kernel_type
@@ -387,7 +387,7 @@ PreparedOp PrepareImpl(
 #endif
 
 #ifdef PADDLE_WITH_XPU_KP
-  if (paddle::platform::is_xpu_place(fluid_kernel_type.place_)) {
+  if (phi::is_xpu_place(fluid_kernel_type.place_)) {
     if (use_xpu_kp_kernel_rt) {
       VLOG(3) << "fluid xpu_kp using rt mode ";
     }
@@ -412,7 +412,7 @@ PreparedOp PrepareImpl(
 #endif
 #ifdef PADDLE_WITH_IPU
   if (kernel_iter == kernels.end() &&
-      paddle::platform::is_ipu_place(fluid_kernel_type.place_)) {
+      phi::is_ipu_place(fluid_kernel_type.place_)) {
     VLOG(3) << "missing IPU kernel: " << op.Type()
             << ", expected_kernel_key:" << fluid_kernel_type
             << ", fallbacking to CPU one!";
@@ -422,7 +422,7 @@ PreparedOp PrepareImpl(
 #endif
 #ifdef PADDLE_WITH_CUSTOM_DEVICE
   if (kernel_iter == kernels.end() &&
-      paddle::platform::is_custom_place(fluid_kernel_type.place_)) {
+      phi::is_custom_place(fluid_kernel_type.place_)) {
     VLOG(3) << "missing " << place.GetDeviceType() << " kernel: " << op.Type()
             << ", expected_kernel_key:" << expected_kernel_key
             << ", fallbacking to CPU one!";
@@ -439,8 +439,8 @@ PreparedOp PrepareImpl(
                                  op.Type(),
                                  KernelTypeToString(fluid_kernel_type)));
 
-  if (!platform::places_are_same_class(fluid_kernel_type.place_,
-                                       dev_ctx->GetPlace())) {
+  if (!phi::places_are_same_class(fluid_kernel_type.place_,
+                                  dev_ctx->GetPlace())) {
     dev_ctx = pool.Get(fluid_kernel_type.place_);
   }
   return PreparedOp(
diff --git a/paddle/fluid/imperative/reducer.cc b/paddle/fluid/imperative/reducer.cc
@@ -39,11 +39,11 @@ void Group::DivNRanks(const platform::DeviceContext &context, int64_t nranks) {
           ? sparse_contents_->GetMutable<phi::SelectedRows>()->mutable_value()
           : dense_contents_.GetMutable<phi::DenseTensor>();
 
-  if (platform::is_gpu_place(tensor->place())) {
+  if (phi::is_gpu_place(tensor->place())) {
 #if defined(PADDLE_WITH_NCCL) || defined(PADDLE_WITH_RCCL)
     DivNRanks(tensor, nranks, context);
 #endif
-  } else if (platform::is_cpu_place(tensor->place())) {
+  } else if (phi::is_cpu_place(tensor->place())) {
     VLOG(4) << "before div 2" << *tensor;
     VLOG(4) << "NDiv for cpu devices : rank = " << nranks;
 #ifdef PADDLE_WITH_HIP
@@ -60,7 +60,7 @@ void Group::DivNRanks(const platform::DeviceContext &context, int64_t nranks) {
         DivNRanksForAllReduce<phi::CPUContext>(tensor, nranks, context));
 #endif
     VLOG(4) << "after div 2" << *tensor;
-  } else if (platform::is_xpu_place(tensor->place())) {
+  } else if (phi::is_xpu_place(tensor->place())) {
 #ifdef PADDLE_WITH_XPU_BKCL
     PADDLE_THROW(
         platform::errors::Unimplemented("DivNRanks is not supported on XPU / "
@@ -226,7 +226,7 @@ void SplitTensorsWithType<platform::XPUDeviceContext>(
 
 void Group::ConcatTensors(const platform::DeviceContext &context) {
   auto place = context.GetPlace();
-  if (platform::is_gpu_place(place)) {  // NOLINT
+  if (phi::is_gpu_place(place)) {  // NOLINT
 #if defined(PADDLE_WITH_NCCL) || defined(PADDLE_WITH_RCCL)
     ConcatTensorsWithType(static_cast<const phi::GPUContext &>(context),
                           dense_tensors_,
@@ -237,7 +237,7 @@ void Group::ConcatTensors(const platform::DeviceContext &context) {
         "Paddle can't concat grad tensors since it's not compiled with NCCL,"
         "Please recompile or reinstall Paddle with NCCL support."));
 #endif
-  } else if (platform::is_xpu_place(place)) {
+  } else if (phi::is_xpu_place(place)) {
 #ifdef PADDLE_WITH_XPU_BKCL
     ConcatTensorsWithType(
         static_cast<const platform::XPUDeviceContext &>(context),
@@ -249,7 +249,7 @@ void Group::ConcatTensors(const platform::DeviceContext &context) {
         "Paddle can't concat xpu grads since it's not compiled with BKCL,"
         "Please recompile or reinstall Paddle with BKCL support."));
 #endif
-  } else if (platform::is_cpu_place(place)) {
+  } else if (phi::is_cpu_place(place)) {
     ConcatTensorsWithType(static_cast<const phi::CPUContext &>(context),
                           dense_tensors_,
                           &dense_contents_,
@@ -262,7 +262,7 @@ void Group::ConcatTensors(const platform::DeviceContext &context) {
 
 void Group::SplitTensors(const platform::DeviceContext &context) {
   auto place = context.GetPlace();
-  if (platform::is_gpu_place(place)) {  // NOLINT
+  if (phi::is_gpu_place(place)) {  // NOLINT
 #if defined(PADDLE_WITH_NCCL) || defined(PADDLE_WITH_RCCL)
     SplitTensorsWithType(static_cast<const phi::GPUContext &>(context),
                          &dense_contents_,
@@ -273,7 +273,7 @@ void Group::SplitTensors(const platform::DeviceContext &context) {
         "Paddle can't split grad tensor since it's not compiled with NCCL,"
         "Please recompile or reinstall Paddle with NCCL support."));
 #endif
-  } else if (platform::is_xpu_place(place)) {
+  } else if (phi::is_xpu_place(place)) {
 #ifdef PADDLE_WITH_XPU_BKCL
     SplitTensorsWithType(
         static_cast<const platform::XPUDeviceContext &>(context),
@@ -285,7 +285,7 @@ void Group::SplitTensors(const platform::DeviceContext &context) {
         "Paddle can't split xpu grad since it's not compiled with BKCL,"
         "Please recompile or reinstall Paddle with BKCL support."));
 #endif
-  } else if (platform::is_cpu_place(place)) {
+  } else if (phi::is_cpu_place(place)) {
     SplitTensorsWithType(static_cast<const phi::CPUContext &>(context),
                          &dense_contents_,
                          &dense_tensors_,
@@ -754,7 +754,7 @@ void Reducer::MarkVarReady(const size_t var_index, const bool is_used_var) {
       }
 
 #ifdef PADDLE_WITH_XPU_BKCL
-      if (platform::is_xpu_place(group_tensor.place())) {
+      if (phi::is_xpu_place(group_tensor.place())) {
         auto dev_ctx = static_cast<platform::XPUDeviceContext *>(
             platform::DeviceContextPool::Instance().Get(place_));
         if (HasGrad(var_index)) {
diff --git a/paddle/fluid/imperative/tracer.cc b/paddle/fluid/imperative/tracer.cc
diff --git a/paddle/fluid/imperative/xccl_context.cc b/paddle/fluid/imperative/xccl_context.cc
