| CARVIEW |
Select Language
HTTP/2 200
date: Sun, 27 Jul 2025 04:30:13 GMT
content-type: text/html; charset=utf-8
cf-ray: 9659666e3c4cc1c9-BLR
cf-cache-status: DYNAMIC
cache-control: private
set-cookie: prov=36499741-de2d-458d-93d0-bf69647c61c0; expires=Mon, 27 Jul 2026 04:30:12 GMT; domain=.stackexchange.com; path=/; secure; httponly
strict-transport-security: max-age=31536000; includeSubDomains
vary: Accept-Encoding
content-security-policy: upgrade-insecure-requests; frame-ancestors 'self' https://stackexchange.com
x-clacks-overhead: GNU Terry Pratchett
x-frame-options: SAMEORIGIN
x-request-guid: e0f83ee6-1f8c-44b8-84e6-29bf3f86ee63
x-worker-origin-response-time: 809000000
x-dns-prefetch-control: off
set-cookie: prov=36499741-de2d-458d-93d0-bf69647c61c0; Path=/; HttpOnly; Domain=stackexchange.com
set-cookie: __cf_bm=0G419MJEZDif2M2L6j42vn9SgPnd0FgDb4aZkuvWOPA-1753590613-1.0.1.1-3Nk9cztVPUKSqkCybBBB4aJi8JVMmNznDCitaqZfZ7PgMOC6iXd8h_oNJWdu.swR0KwBlRlHdX0o7cTsvwsXK9VZ.Tz95eQK9fJwa_2JNoM; path=/; expires=Sun, 27-Jul-25 05:00:13 GMT; domain=.stackexchange.com; HttpOnly; Secure; SameSite=None
set-cookie: _cfuvid=_FASoRGXzpKZJUlMNO0iWa75r8VEmLPoLp.ErhnIXX4-1753590613064-0.0.1.1-604800000; path=/; domain=.stackexchange.com; HttpOnly; Secure; SameSite=None
server: cloudflare
content-encoding: gzip
Newest 'fpga' Questions - Code Review Stack Exchange
Skip to main content
Stack Exchange Network
Stack Exchange network consists of 183 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.
Visit Stack Exchange
Teams
Q&A for work
Connect and share knowledge within a single location that is structured and easy to search.
Learn more about TeamsQuestions tagged [fpga]
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing.
20 questions
- Bountied 0
- Unanswered
- Frequent
- Score
- Trending
- Week
- Month
- Unanswered (my tags)
3
votes
1
answer
231
views
Implements a READ ID command between the iCE40 HX8K and the AT25SF0818 in Verilog
Question
How can I improve my Verilog code?
Context
Flash Read ID Operation
This project is an implimentation of the Read Manufacturer and Device ID (9Fh) operation ...
3
votes
1
answer
96
views
SPI prototype in Verilog: areas for code improvement
I'm working on an SPI in Verilog. I will post what I came up with here. This is an educational project compiled according to the general principle from Wikipedia. There is only one mode - exchange ...
3
votes
1
answer
89
views
Detect when X-axis inputs and Y-axis inputs go high
I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
4
votes
1
answer
150
views
Design and stimulus for a simple Mealy finite state machine
I am trying to code a state machine for the given state diagram:
I
...
1
vote
1
answer
113
views
Clock frequency meter module
The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...
4
votes
1
answer
711
views
LED matrix controller - Verilog
I'm an ECE student. My experience in Verilog and FPGAs is mainly from my digital logic design class. To practice Verilog, I decided to implement a controller for Adafruit LED matrices. It interfaces ...
1
vote
1
answer
181
views
fixed pseudo-random binary sequence (prbs)
On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...
4
votes
1
answer
361
views
Heart beat RTL module
Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...
2
votes
1
answer
2k
views
pseudo-random binary sequence (prbs)
Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
3
votes
1
answer
2k
views
Carry Lookahead Adder - SystemVerilog
I have been learning SystemVerilog before I go back to school and decided to try and implement a Carry Lookahead Adder. As far as I can tell, it works correctly though I haven't tested extensively, ...
2
votes
0
answers
411
views
a simple interrupt polling program due to AXI DMA IP
The program transfers a data array from a Zynq-7000 PS DDR to a BRAM IP (block RAM) memory in a PL part of a FPGA due to a PL AXI DMA IP. Inferring a xilinx axi dma driver (not scatter-gather mode), ...
6
votes
1
answer
822
views
VGA sync generator for 640x480@60Hz
I wrote my first module in Verilog. The purpose is to maintain two counters and emit signals corresponding to VGA's HSync and VSync, as well as HBlank and VBlank pulses to be used by a video ...
7
votes
1
answer
133
views
Signal output on Raspberry Pi that acts as input for FPGA
Problem
I'm writing a verilog program that does the trapezoidal integration method (where a review is also welcome, wink wink). But turns out you need input for these kind of things, so in the overly ...
6
votes
2
answers
1k
views
Verilog implementation of trapezoidal integration method
Any and all comments are welcome in this review.
##Problem
I've been doing a lot with numerical integration methods recently and have mostly been programming in Python. But, speedups and FPGAs are ...
6
votes
2
answers
2k
views
Simple SystemVerilog AXI controller
I have a more long-term project I'm using to learn FPGA/HDL, and this is first sub-component of it used for testing. I'm targeting Zynq device.
I'd like to create a component which creates an image. ...
- The Overflow Blog
-
-
- Featured on Meta
-
-
Related Tags
verilog × 14
hdl × 9
system-verilog × 7
c × 4
embedded × 3
rtl × 2
vhdl × 1
beginner × 1
assembly × 1
raspberry-pi × 1
python-3.x × 1
python × 1
object-detection × 1
device-driver × 1
more related tags
Hot Network Questions
- Statistics – Linear Inference – What is the moment generating function of non-central t-distribution?
- Why does Gaza Humanitarian Foundation (GHF) not distribute more food in Gaza?
- I am looking for a French mathematician who contributed to complex analysis
- Regenerative cooling of rocket engine turbine's blades
- When and why is fwait necessary when using the 8087 coprocessor?
- Is it okay to email researchers if I’m a high school student?
- Will a reinforced 1" concrete slab be durable?
- A national poll of 1000 French returns 25% of "Yes". Is it enough to say that it's quite impossible locally to be 0%, if we don't know the variance?
- How to extend an MDF shelf?
- What Isp can be gotten from a napthalene (mothball) hot gas thruster? Did it work in space?
- Moving multiplying cells away
- Story that taught cryptography in the form of a manga
- Most practical way to determine concentration of reducing sugar in frozen French fries?
- What is the best interpretation of Psalm 6:4? Does "Turn" or "Return" capture the intended meaning?
- When was the last time all humans were on the ground not in the air?
- Early Sailing days in September 1066... Could Harold defeat William at Hastings, if it happened before Stamford Bridge?
- How can I turn the text in a PNG file back into text layer?
- Tracking stored procedure performance metrics
- Why does the node Bounding Box suddenly produce a different result in version 4.5?
- Why is 0.0 printed as 0.00001 when rounding upward?
- I don't understand Photos Library.photoslibrary
- Can a minor run a business by having an adult act on their behalf?
- What does this word "ahn-shdah-heh" mean?
- How much of a really big a spaceship could a nuke take out?