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Newest 'verilog' Questions - Code Review Stack Exchange
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Learn more about TeamsQuestions tagged [verilog]
Verilog is a hardware description language (HDL) maintained by Accellera Systems Initiative and standardized as 'IEEE Standard 1364'.
40 questions
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3
votes
1
answer
111
views
SystemVerilog: LED blinker control logic
I built this simple blinker in SystemVerilog and would very much like some help to make it better:
control.sv
...
4
votes
1
answer
87
views
I2C master interacting with ADC IC
The code is for an I2C master that interacts with an ADC IC (ADS1115).
Is there a more practical way of seeing what the internal regs and wires are doing in testbench, without creating a ports for ...
4
votes
1
answer
243
views
I2C serial communication protocol for university project
For now, I have only implemented a simple I2C protocol where only the master transmits the data. Also there is ack_bit for the I2C Address only. For state 5, i.e.,...
7
votes
1
answer
273
views
RISCV ALU Implementation in SystemVerilog
This will be first of many things I will submit during my journey of self (re)learning CPU design.
I have ALU implementation for RiscV base instruction. I am not fully sure what I am looking
for, but ...
3
votes
1
answer
231
views
Implements a READ ID command between the iCE40 HX8K and the AT25SF0818 in Verilog
Question
How can I improve my Verilog code?
Context
Flash Read ID Operation
This project is an implimentation of the Read Manufacturer and Device ID (9Fh) operation ...
3
votes
1
answer
96
views
SPI prototype in Verilog: areas for code improvement
I'm working on an SPI in Verilog. I will post what I came up with here. This is an educational project compiled according to the general principle from Wikipedia. There is only one mode - exchange ...
2
votes
1
answer
81
views
Sensored BLDC commutation controller testbench code
This is testbench code for a combinational logic circuit with 6 input variables and 6 output variables. The 3 binary HS (hall sensor) input variables are signals given by the BLDC motors' sensors that ...
3
votes
1
answer
112
views
Sensored BLDC Commutation Controller code
For context, I'm using a maxII epm240 cpld, and I want to be able to program this to FPGAs too. I know I could build this in a typical state machine fashion since a sensored BLDC motor controller is a ...
3
votes
1
answer
89
views
Detect when X-axis inputs and Y-axis inputs go high
I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
4
votes
1
answer
150
views
Design and stimulus for a simple Mealy finite state machine
I am trying to code a state machine for the given state diagram:
I
...
2
votes
1
answer
232
views
ROM memory in SystemVerilog and cocotb
The Verilog module describes a ROM memory. An initialization file is needed for the INIT_FILE parameter.
Below are Makefile, gtkwave.tcl to launch gtkwave, ...
1
vote
1
answer
113
views
Clock frequency meter module
The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...
2
votes
1
answer
289
views
SystemVerilog implementation of an N-bit prefix adder logic design
I want some feedback about my code (anything is welcome). It is working, but it feels like a clumsy implementation. Because I am self-learning from a book without an answers section, it becomes ...
4
votes
2
answers
611
views
Simple GPIO design module in SystemVerilog
I am designing a very crude general-purpose input/output (GPIO) module to provide IO pin control to a RISC-V (like) architecture microprocessor I am currently playing with.
This is the code so far:
<...
2
votes
1
answer
82
views
Variable output stream delay no shift register
I'm looking to improve my Verilog coding form by reducing utilization and learning any tricks more experienced Verilogers may know.
This module takes in a pulse data stream with pulses occurring ...
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