| CARVIEW |
Select Language
HTTP/2 200
date: Sun, 27 Jul 2025 09:55:18 GMT
content-type: text/html; charset=utf-8
cf-ray: 965b42a5781cc18d-BLR
cf-cache-status: DYNAMIC
cache-control: private
set-cookie: prov=16435445-ea7b-4218-8824-c30b055a7830; expires=Mon, 27 Jul 2026 09:55:18 GMT; domain=.stackexchange.com; path=/; secure; httponly
strict-transport-security: max-age=31536000; includeSubDomains
vary: Accept-Encoding
content-security-policy: upgrade-insecure-requests; frame-ancestors 'self' https://stackexchange.com
x-clacks-overhead: GNU Terry Pratchett
x-frame-options: SAMEORIGIN
x-request-guid: 78c4bbba-b67b-4969-b371-d0956b6a6f08
x-worker-origin-response-time: 833000000
x-dns-prefetch-control: off
set-cookie: prov=16435445-ea7b-4218-8824-c30b055a7830; Path=/; HttpOnly; Domain=stackexchange.com
set-cookie: __cf_bm=1Jm5MKia1nXVTsbioo2YMwUUBZkdbt74BPRennk.wI8-1753610118-1.0.1.1-XSFsZs4p8V_N5I1g8Vz6k1ycxlWB03ZUtttrThX4DWFW1XhSIrVwZCsGASxu1NtXOT6iiZpJTsaerBEly_NE_6o66N_4NKNHUglXGdcKyIY; path=/; expires=Sun, 27-Jul-25 10:25:18 GMT; domain=.stackexchange.com; HttpOnly; Secure; SameSite=None
set-cookie: _cfuvid=wzRvJ0vXwmnnkLPH3xTCOvGx4VU1J2FhHmK5v3xf7nE-1753610118851-0.0.1.1-604800000; path=/; domain=.stackexchange.com; HttpOnly; Secure; SameSite=None
server: cloudflare
content-encoding: gzip
Newest 'system-verilog' Questions - Code Review Stack Exchange
Skip to main content
Stack Exchange Network
Stack Exchange network consists of 183 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.
Visit Stack Exchange
Teams
Q&A for work
Connect and share knowledge within a single location that is structured and easy to search.
Learn more about TeamsQuestions tagged [system-verilog]
SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.
15 questions
- Bountied 0
- Unanswered
- Frequent
- Score
- Trending
- Week
- Month
- Unanswered (my tags)
3
votes
1
answer
111
views
SystemVerilog: LED blinker control logic
I built this simple blinker in SystemVerilog and would very much like some help to make it better:
control.sv
...
4
votes
1
answer
87
views
I2C master interacting with ADC IC
The code is for an I2C master that interacts with an ADC IC (ADS1115).
Is there a more practical way of seeing what the internal regs and wires are doing in testbench, without creating a ports for ...
4
votes
1
answer
243
views
I2C serial communication protocol for university project
For now, I have only implemented a simple I2C protocol where only the master transmits the data. Also there is ack_bit for the I2C Address only. For state 5, i.e.,...
7
votes
1
answer
273
views
RISCV ALU Implementation in SystemVerilog
This will be first of many things I will submit during my journey of self (re)learning CPU design.
I have ALU implementation for RiscV base instruction. I am not fully sure what I am looking
for, but ...
3
votes
1
answer
231
views
Implements a READ ID command between the iCE40 HX8K and the AT25SF0818 in Verilog
Question
How can I improve my Verilog code?
Context
Flash Read ID Operation
This project is an implimentation of the Read Manufacturer and Device ID (9Fh) operation ...
3
votes
1
answer
89
views
Detect when X-axis inputs and Y-axis inputs go high
I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
2
votes
1
answer
232
views
ROM memory in SystemVerilog and cocotb
The Verilog module describes a ROM memory. An initialization file is needed for the INIT_FILE parameter.
Below are Makefile, gtkwave.tcl to launch gtkwave, ...
1
vote
1
answer
113
views
Clock frequency meter module
The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...
2
votes
1
answer
289
views
SystemVerilog implementation of an N-bit prefix adder logic design
I want some feedback about my code (anything is welcome). It is working, but it feels like a clumsy implementation. Because I am self-learning from a book without an answers section, it becomes ...
4
votes
2
answers
611
views
Simple GPIO design module in SystemVerilog
I am designing a very crude general-purpose input/output (GPIO) module to provide IO pin control to a RISC-V (like) architecture microprocessor I am currently playing with.
This is the code so far:
<...
3
votes
2
answers
1k
views
Accessing multiple dynamic libraries with the same extern C methods
I have multiple pre-compiled dynamic libraries that use the same extern "C" function names. The functions can behave differently for each dynamic library. ...
1
vote
1
answer
181
views
fixed pseudo-random binary sequence (prbs)
On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...
4
votes
1
answer
361
views
Heart beat RTL module
Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...
2
votes
1
answer
2k
views
pseudo-random binary sequence (prbs)
Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
6
votes
2
answers
2k
views
Simple SystemVerilog AXI controller
I have a more long-term project I'm using to learn FPGA/HDL, and this is first sub-component of it used for testing. I'm targeting Zynq device.
I'd like to create a component which creates an image. ...
- The Overflow Blog
-
-
- Featured on Meta
-
-
Related Tags
verilog × 14
fpga × 7
hdl × 5
beginner × 2
embedded × 2
rtl × 2
python-3.x × 1
python × 1
object-detection × 1
library × 1
io × 1
dynamic-loading × 1
c++11 × 1
c++ × 1
more related tags
Hot Network Questions
- Anonymizing a submission for double-blind review
- Confusing/incorrect sentence in proof of Zorn's Lemma in Lang's "Real and Functional Analysis"
- “Unclear step in a math book for entertainment”
- When and why is fwait necessary when using the 8087 coprocessor?
- I am looking for a French mathematician who contributed to complex analysis
- How can I turn the text in a PNG file back into text layer?
- Not being introduced to the team – should I ask for it?
- When was the last time all humans were on the ground not in the air?
- How much of a really big a spaceship could a nuke take out?
- Kepler's first law proof error - can anyone help me see what the error is?
- Class for validating code in different Conda environments with PyTorch
- Humans on alien planet get tailed by silent humanoids
- Why is time reversal not a natural part of the Galilean group?
- Question about relativity of simultaneity vs signal delay
- Forces applied to a car hood while driving
- Heretofore I think I have been using 'heretofore' incorrectly
- Why does Gaza Humanitarian Foundation (GHF) not distribute more food in Gaza?
- How to put commutative symbol in a commutative diagram?
- How do Francophones hear "ChatGPT"?
- Did Denmark report that 64% Palestinian refugees from 1992 received serious fines or jail time?
- Does SZNUD3160 really eliminate the need for diode?
- Lower bound on ratio of expected maxima of i.i.d. samples from distribution on [0,1]
- Tracking stored procedure performance metrics
- JK flip-flop timing diagram: is Wikipedia correct?